Back to results
US 6,369,624 B1Granted
Programmable phase shift circuitry
AssigneeAltera Corporation
InventorsBonnie I. Wang, Joseph Huang, Chiakang Sung, Xiaobao Wang, In Whan Kim, Wayne Yeung, Khai Nguyen
Life of this patent
Estimating the term…
Abstract
A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.
Claims26
A circuit comprising:
- a phase detector circuit receiving a reference clock signal;
- a charge pump circuit coupled to the phase detector circuit;
- a voltage controlled oscillator coupled to the charge pump, wherein the voltage controlled oscillator generates a plurality of voltage controlled oscillator outputs;
- and
- a first multiplexer coupled to the voltage controlled oscillator, wherein the multiplexer selects one of the voltage controlled oscillator outputs as a first clock output,
- wherein the voltage controlled oscillator output comprises a plurality of delay stages, a delay stage comprising:
- a second multiplexer having inputs coupled to a first of the voltage controlled oscillator outputs, and a second of the voltage controlled oscillator outputs;
- a first buffer coupled between the second multiplexer and a third of the voltage controlled oscillator outputs;
- a third multiplexer having inputs coupled to the third of the voltage controlled oscillator outputs and a fourth of the voltage controlled oscillator outputs;
- and
- a second buffer coupled between the third multiplexer and the second of the voltage controlled oscillator outputs.
8 more elements
A programmable logic integrated circuit comprising:
- a programmable interconnect structure;
- a plurality of logic array blocks, configurable to perform logic function, programmably coupled to the programmable interconnect structure;
- a phase locked loop circuit generating an internal clock signal that is programmably coupled to the logic array blocks, wherein a phase shift between a reference clock signal and the internal clock signal is user selectable,
- wherein the phase locked loop circuit comprises:
- a phase detector circuit coupled to the reference clock signal;
- a charge pump coupled to the phase detector circuit;
- and
- a voltage controlled oscillator coupled to the charge pump wherein the voltage controlled oscillator generates a plurality of clock outputs, and the internal clock signal is a first of the plurality of clock outputs;
- and
- a first multiplexer circuit coupled to the plurality of clock outputs, wherein the first multiplexer circuit selectively couples one of the plurality of clock outputs to the phase detector circuit,
- wherein the voltage controlled oscillator output comprises a plurality of delay stages, a delay stage comprising:
- a second multiplexer circuit having inputs coupled to a first of the voltage controlled oscillator outputs, and a second of the voltage controlled oscillator outputs;
- a first buffer coupled between the second multiplexer circuit and a third of the voltage controlled oscillator outputs;
- a third multiplexer circuit having inputs coupled to the third of the voltage controlled oscillator outputs and a fourth of the voltage controlled oscillator outputs;
- and
- a second buffer coupled between the third multiplexer circuit and the second of the voltage controlled oscillator outputs.
13 more elements
Dependencies are inferred from the claim text.