Method for forming a semiconductor device

A method for forming a semiconductor device comprising:

• forming a conductive layer over a semiconductor substrate, wherein the semiconductor substrate includes a first dopant type;
• forming a dummy layer over the conductive layer;
• removing portions of the dummy layer to form a dummy feature;
• forming a first spacer, wherein a combination of the first spacer and the dummy feature forms a first patterned feature;
• removing the dummy feature from the first patterned feature to form a second patterned feature;
• doping a first region of the semiconductor substrate with a second dopant type before removing the dummy feature;
• removing portions of the conductive layer that are not masked by the second patterned feature to form a gate electrode;
• removing a remaining portion of the first spacer;
• forming a second spacer adjacent the gate electrode;
• doping a second region of the semiconductor substrate adjacent the gate electrode with a third dopant type before forming a second spacer;
• and
• doping a third region of the semiconductor substrate adjacent the second spacer with a fourth dopant type after forming a second spacer.

A method for forming a semiconductor device comprising:

• forming a dielectric layer over a semiconductor substrate, wherein the semiconductor substrate includes a first dopant type;
• forming a conductive layer over the dielectric layer;
• forming a dummy layer over the conductive layer;
• removing portions of the dummy layer to form a dummy feature having a sidewall;
• forming a first spacer adjacent the sidewall, wherein the dummy feature and the first spacer are formed from different materials and a combination of the dummy feature and the first spacer forms a first patterned feature;
• doping a first region of the semiconductor substrate adjacent the first patterned feature with a second dopant type, wherein the first dopant type and the second dopant type are from a same family of dopant types;
• removing the dummy feature from the first patterned feature to define a second patterned feature;
• removing portions of the conductive layer that are not masked by the second patterned feature to form a gate electrode;
• removing a remaining portion of the first spacer;
• doping a second region of the semiconductor substrate with a third dopant type to form source/drain regions adjacent the gate electrode, wherein the third dopant type includes dopants from a family of dopant types that is opposite the first dopant type and the second dopant type, and wherein a concentration of dopant species in a source region and a concentration of dopant species in a drain region are a different concentration;
• and
• doping a third region of the semiconductor substrate with a fourth dopant type to form extension regions;
• and
• forming spacers adjacent the gate electrode after doping the third region and prior to doping portions of the semiconductor substrate with a third dopant type to form source/drain regions, wherein the fourth dopant type and the third dopant type are from a same family of dopant types.