Gate-voltage controlled electrostatic discharge protection circuit

Abstract

A gate-voltage controlled ESD protection circuit is provided, which is designed to couple between an input port and an IC device having an inverter coupled to the internal circuit of the IC device for the purpose of protecting the IC device against ESD stress. The first potential drop subcircuit is capable of allowing the PMOS transistor to be immediately switched into the conductive state in the event that a negative ESD voltage of a large magnitude is being applied to the input port. Similarly, the second potential drop subcircuit is capable of allowing the NMOS transistor to be immediately switched into the conductive state in the event that a positive ESD voltage of a large magnitude is being applied to the input port. The characteristic structure of the ESD protection circuit can help the PMOS and NMOS transistors in the ESD protection circuit to provide the desired ESD protection without being affected by breakdown of the thin oxide layer in the inverter, as in the prior art.

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