Semiconductor device having bipolar transistor and MOS transistor

Abstract

A semiconductor device in which a bipolar transistor and a MOS transistor are formed in a common element region, which can prevent a circuit layout pattern from being large due to a wiring. A semiconductor device having an element region formed by the N−-type layer, which is isolated and insulated from the other regions. A P+-type base region, an N−-type emitter region, an N+-type collector region, and a P+-type excess carrier removing region for removing excess carrier in the P+-type base region, are commonly formed in particular one N−-type layer. Thus, a bipolar transistor is defined. Furthermore, a gate oxide film is formed on the surface of the N−-type layer where between the P+-type base region and the P+-type excess carrier removing region. A polysilicon layer is formed on the gate oxide film. Thus, a P+-type MOS transistor is defined by using the P+-type base region as a source and the P+-type excess carrier removing region a drain. The P+-type base region, the P+-type excess carrier removing region, the N−-type emitter region, the N+-type collector region, and the polysilicon layer are respectively connected to metallic electrodes. Since the bipolar transistor and the MOS transistor are commonly formed in an element region, and one of regions is commonly used, it can prevent a circuit layout pattern from being large due to a wiring for connecting the bipolar transistor and the MOS transistor.

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