Method of determining lethality of defects in circuit pattern inspection method of selecting defects to be reviewed and inspection system of circuit patterns involved with the methods

A method of inspecting defects of circuit patterns formed on a substrate, comprising the steps of:

• (1) inputting area coordinate data of the circuit patterns;
• (2) inputting data regarding lethality of defects existing on the circuit patterns;
• (3) inputting coordinate data of defects detected on the circuit patterns and sizes of the defects;
• (4) identifying areas to which the defects belong, from the coordinate data of the defects;
• (5) comparing sizes of the defects with the data regarding the lethality of the defects by using the coordinate data of the defects to determine the lethality of the detected defects;
• and
• (6) displaying information of lethality of the detected defects determined in the step of comparing.

A method of inspecting defects of circuit patterns formed on a substrate, comprising the steps of:

• inputting inspection data of the defects existing on the circuit patterns inspected by an inspection apparatus;
• processing the inputted inspection data to select candidate defects to be reviewed;
• determining the defects to be reviewed among the selected candidate defects;
• and
• outputting information relating to the determined defects to be reviewed,
• wherein the selected candidate defects are lethality defects.

A method of inspecting defects of circuit patterns formed on a substrate comprising the steps of:

• (1) accepting area coordinate data of the circuit patterns;
• (2) accepting data to determine the lethality of the defects;
• (3) accepting coordinate data of the defects detected on the circuit patterns and sizes of the defects;
• (4) identifying areas to which the defects belong, from the coordinate data of the defects detected on the circuit patterns;
• (5) determining lethality of the detected defects by using information of the coordinate data and size data of the defects;
• and
• (6) selecting the defects to be reviewed among the defects whose lethality are determined.

An apparatus for inspecting defects of circuit patterns formed on a substrate, comprising:

• a first memory to store inspection data of the defects existing on the circuit patterns detected by the inspection apparatus;
• a second memory to store a data for determining lethality of the defects;
• a processor to process the inspection data stored in the first memory;
• and
• means to determine the lethality of the defects corresponding to the inspection data by using the data stored in the second memory and the inspection data processed by the processor.

An apparatus for inspecting defects of circuit patterns formed on a substrate, comprising:

• a first means to store area coordinate data of the circuit patterns;
• a second means to store data to determine lethality of defects existing on the circuit patterns;
• a third means to store coordinate data of defects detected on the circuit patterns and sizes of the defects;
• a fourth means to identify the areas to which the defects belong, from the coordinate data of the defects stored in the third means;
• and
• a fifth means to compare sizes of the defects detected with the data to determine the lethality of the defects produced in the areas on the circuit patterns where the defects belong to thereby determine the lethality of the defects.

An apparatus for inspecting defects of circuit patterns formed on a substrate, comprising:

• a first memory to store data of the defects existing on the circuit patterns, which are detected by an inspection apparatus;
• a second memory to store data to determine a lethality of defects;
• a first processor to determine the lethality of the defects stored in the first memory by using the data stored in the second memory;
• and
• a second processor to select defects to be reviewed among defects whose lethality is determined by the first processor.

An apparatus for inspecting defects of circuit pasterns formed on a substrate, comprising:

• a first memory to store area coordinate data of the circuit patterns;
• a second memory to store data to determine the lethality of the defects existing on the circuit patterns;
• a third memory to store coordinate data of defects detected on the circuit patterns and sizes of the defects;
• means to identify the areas to which the defects belong, from the coordinate data of the defects stored in the third memory;
• means to calculate the ratios of the sizes of the defects detected against the data to determine the lethality of the defects produced in the areas on the circuit patterns to which the defects belong;
• and
• means to select defects to be reviewed among the defects calculated by the means to calculate.