Nonvolatile ferroelectric memory device and method for driving same

A nonvolatile ferroelectric memory device provided with a plurality of sub cell arrays consisting of a plurality of main cells and at least one reference cell, wherein the reference cell of any one of the sub cell arrays is operated along with a main cell of a neighboring sub cell array, the nonvolatile ferroelectric memory device comprising:

• first, second and third impurity regions selectively formed in a semiconductor substrate;
• a first gate electrode formed on the substrate between the first and second impurity regions;
• a second gate electrode formed on the substrate between the second and third impurity regions;
• a plurality of ferroelectric capacitors electrically insulated from the first and second gate electrodes;
• a conducting layer for selectively connecting ferroelectric capacitors to the second impurity region;
• and
• a bitline electrically insulated from the conducting layer and electrically connected with the first impurity region.

A nonvolatile ferroelectric memory device provided with a plurality of sub cell arrays consisting of a plurality of main cells and at least one reference cell, wherein the reference cell of any one of the sub cell arrays is operated along with a main cell of a neighboring sub cell array, the nonvolatile ferroelectric memory device comprising:

• a first transistor having a gate connected with a reference wordline and a drain connected with a bitline;
• a second transistor controlled by a reference bitline equalizer signal applied to a gate, having a drain connected with a source of the first transistor and a source connected with a ground voltage terminal;
• and
• a plurality of ferroelectric capacitors having first terminals, second terminals, and ferroelectric layers formed between the first terminals and the second terminals, the first terminals being commonly connected with the source of the first transistor, and the second terminals being commonly connected.

A method for driving a nonvolatile ferroelectric memory device that includes a plurality of sub cell arrays consisting of a plurality of main cells and at least one reference cell, the reference cell of any one of the sub cell arrays being operated along with a main cell of a neighboring sub cell array and each cell having one transistor and one ferroelectric capacitor among a bitline, a wordline, and a plate line, the method comprising the steps of:

• activating the wordline and the plate line in an active period of one cycle;
• inactivating the wordline;
• activating a sensing amplifier;
• inactivating the plate line;
• activating the wordline when a precharge period starts;
• and
• inactivating the wordline before the precharge period ends.