MOS integrated circuit device operating with low power consumption
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsEiichi Teraoka, Toyohiko Yoshida
Life of this patent
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Abstract
In accordance with selection signals corresponding to an operation mode from a mode detection circuit, the voltage levels of back gate voltages applied to the back gates of MOS transistors included in internal circuitry are selected, by the selection signals, among the voltages from voltage generation circuits for generating a plurality of voltages having different voltage levels. The threshold voltage and the drive current of the MOS transistor are adjusted in accordance with the operation mode, and the semiconductor integrated circuit device which operates at high speed with low current consumption can be achieved.
Claims7
A semiconductor integrated circuit device, comprising:
- internal circuitry including, as a component, a first insulated gate type field effect transistor having a source receiving a prescribed voltage and a back gate and a second insulated gate type field effect transistor different in conductivity type from said first insulated gate type field effect transistor and having a source receiving a predetermined voltage and a back gate, and operable in a plurality of operation modes;
- first bias voltage generation circuitry for generating a plurality of bias voltages including voltages different in voltage level and in polarity with respect to said prescribed voltage from each other;
- second bias voltage generation circuitry for generating a plurality of bias voltages including voltages different in voltage level in polarity with respect to said predetermined voltage from each other;
- operation mode detection circuitry for detecting an operation mode of said internal circuitry and generating a selection signal corresponding to the detected operation mode;
- first bias voltage selection circuitry for receiving the selection signal from said operation mode detection circuitry, selecting one of said plurality of bias voltages from said first bias voltage generation circuitry in accordance with the received selection signal, and applying the selected bias voltage to the back gate of said first insulated gate type field effect transistor;
- and
- second bias voltage selection circuitry for receiving the selection signal from said operation mode detection circuitry, selecting one of said plurality of bias voltages from said second bias voltage generation circuitry in accordance with the received selection signal and applying the selected bias voltage to the back gate of said second insulated gate type field effect transistor.
Dependencies are inferred from the claim text.