Semiconductor device and method of manufacturing the same
AssigneeNEC Corporation
InventorHidetaka Natsume
Life of this patent
Estimating the term…
Abstract
An SRAM cell is arranged in a semiconductor device. A metal oxide semiconductor field effect transistor is arranged in the SRAM cell. An interlayer insulating film is formed on the metal oxide semiconductor field effect transistor. A load resistor conductive layer is formed on the interlayer insulating film. In addition, a wiring conductive layer which connects the gate electrode of the metal oxide semiconductor field effect transistor to the load resistor conductive layer is provided. The resistance of the wiring conductive layer is lower than the resistance of the load resistor conductive layer. A side wall is formed between the load resistor conductive layer and the wiring conductive layer.
Claims21
A semiconductor device, comprising:
- a high resistance load type static random access memory cell, said high resistance load type static random access memory cell comprising:
- a low resistance polysilicon layer, wherein a portion of said low resistance polysilicon layer provides interior wiring;
- a high resistance polysilicon layer, wherein a portion of said high resistance polysilicon layer provides a resistance region having a predetermined length, said high resistance polysilicon layer provided on said low resistance polysilicon layer except for said resistance region, said high resistance polysilicon layer contacting only the upper surface of said low resistance polysilicon layer, and said resistance region disposed above a diffusion region of an MOS transistor;
- and
- a side wall spacer provided at a side surface of said low resistance polysilicon layer, said side wall spacer interposed between said low resistance polysilicon layer and said high resistance polysilicon layer.
A semiconductor device, comprising:
- a static random access memory cell, said static random access memory cell comprising:
- a metal oxide semiconductor field effect transistor;
- an interlayer insulating film provided on said metal oxide semiconductor field effect transistor;
- a first conductive wiring provided on said interlayer insulating film;
- a second conductive wiring;
- a load resistor conductive layer provided on said interlayer insulating film and connected to said first conductive wiring, said load resistor conductive layer being connected to a gate electrode of said metal oxide semiconductor field effect transistor by said second conductive wiring, the resistance of said second conductive wiring being lower than the resistance of said load resistor conductive layer;
- a first side wall spacer provided between said load resistor conductive layer and said first conductive wiring;
- and
- a second side wall spacer provided between said load resistor conductive layer and said second conductive wiring.
Dependencies are inferred from the claim text.