CMOS fabrication process with differential rapid thermal anneal scheme
AssigneeAdvanced Micro Devices, Inc.
InventorBin Yu
Life of this patent
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Abstract
A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dual amorphization technique. The technique creates a shallow amorphous region and a deep amorphous region. The shallow amorphous region is between 10-15 nm below the top surface of the substrate, and the deep amorphous region is between 150-200 nm below the top surface of the substrate. The process can be utilized for P-channel or N-channel metal oxide semiconductor field effect transistors (MOSFETs). In the case of a P-channel MOSFET, a nitrogen barrier is formed in the P-channel gate prior to p+ doping. Annealing the gate conductor is done in a step separate from the source/drain region annealing step.
Claims23
A method of providing field effect transistors, the method comprising:
- providing a gate material over a semiconductor substrate;
- providing a first mask pattern having first apertures associated with N-type dopant gate conductors;
- providing N-type dopants through the first apertures;
- providing a second mask pattern having second apertures associated with P-type gate conductors;
- providing nitrogen type dopants through the second apertures to form a nitrogen barrier in the material above the semiconductor substrate;
- providing P-type dopants through the second apertures to the material;
- providing a third mask over the material, the third mask having features above the locations associated with the first apertures and the second apertures;
- removing the portions of the material in accordance with the features, whereby N-type gate conductors and P-type gate conductors are formed;
- annealing the N-type gate conductors and the P-type gate conductors;
- doping the substrate for source and drain regions;
- and
- annealing the substrate to form the source and drain regions.
A method of providing field effect transistors, the method comprising the steps of:
- providing a layer of undoped polysilicon over a substrate;
- providing a first mask pattern above the layer, the first mask pattern having first apertures associated with N-type dopant gate conductors;
- providing N-type dopants through the first apertures to the layer;
- providing a second mask pattern above the layer, the second mask pattern having second apertures associated with P-type gate conductors;
- providing nitrogen type dopants through the second apertures to form a nitrogen barrier in the layer above the semiconductor substrate;
- providing P-type dopants through the second apertures to the layer;
- providing a third mask over the layer, the third mask having features above locations associated with the first apertures and the second apertures;
- removing portions of the layer in accordance with the features, whereby the N-type gate conductors and the P-type gate conductors are formed;
- annealing the N-type gate conductors or the P-type gate conductors;
- doping the substrate for source and drain regions;
- and
- annealing the substrate to form the source and drain regions.
A method of providing field effect transistors, the method comprising:
- providing a gate material over a semiconductor substrate;
- providing a first mask pattern having first apertures associated with N-type dopant gate conductors;
- implanting N-type dopants through the first apertures;
- providing a second mask pattern having second apertures associated with P-type gate conductors;
- implanting nitrogen through the second apertures to form a nitrogen barrier in the material above the semiconductor substrate;
- implanting P-type dopants through the second apertures;
- providing a third mask over the material, the third mask having features above the locations of the first apertures and the second apertures;
- removing portions of the material in accordance with the features, whereby the N-type gate conductors and the P-type gate conductors are formed;
- and
- annealing the gate conductors.
A method of providing a field effect transistors, the method comprising:
- providing a gate material over a semiconductor substrate;
- providing a first mask pattern having first apertures associated with N-type dopant gate conductors providing N-type dopants through the first apertures;
- providing a second mask pattern having second apertures associated with P-type gate conductors;
- providing nitrogen type dopants through the second apertures to form a nitrogen barrier in the material above the semiconductor substrate;
- providing P-type dopants through the second apertures;
- prividing a third mask over the material, the third mask having features above the locations of the first apertures and the second apertures;
- removing portions of the material in accordance with the features;
- whereby the N-type gate conductors and the P-type gate conductors are formed;
- annealing the N-type and the P-type gate conductors;
- amorphizing the substrate for source and drain extensions in the substrate;
- doping the substrate for source and drain extensions;
- providing spacers for the N-type and the P-type gate conductors;
- amorphizing the substrate for deep source and drain regions in the substrate;
- doping the substrate for the deep source and drain regions;
- and
- annealing the substrate.
Dependencies are inferred from the claim text.