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US 6,333,239 B1Granted
Processes for reduced topography capacitors
AssigneeInternational Business Machines Corporation
InventorsJohn M. Aitken, Alvin W. Strong
Life of this patent
Estimating the term…
Abstract
A planarized interleaved capacitor for use with a substrate. The capacitor has a plurality of planarized metal layers formed above the substrate, at least one dielectric layer disposed between the plurality of planarized metal layers, and at least one insulator layer disposed over one of the plurality of metal layers.
Claims24
A process for fabricating a planarized interleaved capacitor comprising the steps of:
- (a) forming at least three planarized metal layers over one another;
- (b) disposing at least one dielectric layer between each of the at least three planarized metal layers;
- (c) connecting a first one of the at least three planarized metal layers to a third one of the at least three planarized metal layers;
- and
- (d) disposing at least one insulator layer over one of the at least three metal layers.
2 more elements
A process for fabricating a planarized interleaved capacitor comprising the steps of:
- (a) disposing a first insulator;
- (b) forming a first area in the first insulator;
- (c) disposing a first metal layer as an electrode in the first area;
- (d) forming a dielectric above at least a portion of the first metal layer;
- and
- (e) forming a second metal layer over the dielectric.
3 more elements
A process for fabricating a planarized interleaved capacitor comprising the steps of:
- (a) disposing a first insulator;
- (b) forming a first area in the first insulator;
- (c) disposing a first metal layer as an electrode above the top surface of the first insulator;
- (d) forming a dielectric above at least a portion of the first metal layer;
- (e) forming a second insulator above the dielectric;
- (f) forming a second area in the dielectric and the second insulator;
- and
- (g) forming a second metal layer in at least a portion of the second area.
5 more elements
A process for fabricating a planarized interleaved capacitor comprising the steps of:
- (a) disposing a first insulator;
- (b) planarizing the first insulator;
- (c) forming a first area in the first insulator;
- (d) disposing a first metal layer in the first area;
- (e) planarizing the first metal layer and the first insulator;
- (f) disposing a second insulator above the first metal layer;
- (g) forming a second area in the second insulator;
- (h) disposing a first dielectric above the second area;
- (i) planarizing the first dielectric and the second insulator;
- (j) forming a third area in the first dielectric and the second insulator;
- and
- (k) disposing a second metal layer above the insulator and the third area of the dielectric.
9 more elements
A process for fabricating a planarized interleaved capacitor comprising the steps of:
- (a) disposing a first insulator;
- (b) forming a first contact area in the first insulator;
- (c) disposing a first metal level within the first contact area;
- (d) planarizing the first metal layer and the first insulator;
- (e) disposing a first dielectric above the first metal level and the first insulator;
- (f) disposing a second insulator above the first dielectric;
- (g) forming a second contact area in the first dielectric and the second insulator;
- (h) disposing a second metal layer within the second contact area;
- (i) planarizing the second metal layer and the second insulator;
- (j) disposing a second dielectric above the second metal level and the second insulator;
- (k) forming a third insulator above the second dielectric;
- (l) forming a third contact area in the second dielectric and the third insulator;
- (m) disposing a third metal layer above the third insulator and the third contact area of the dielectric;
- and
- (n) planarizing the third metal layer and the third insulator.
12 more elements
A process for fabricating a planarized interleaved capacitor comprising the steps of:
- (a) forming at least three planarized insulator layers over one another;
- (b) forming a planarized metal layer within respective ones of the at least three planarized insulator layers;
- (c) connecting a first one of the planarized metal layers to a third one of the planarized metal layers;
- and
- (d) disposing at least one dielectric layer between adjacent ones of the planarized metal layers.
2 more elements
A process for fabricating a planarized interleaved capacitor comprising the steps of:
- (a) disposing a first insulator;
- (b) forming a first area in the first insulator;
- (c) disposing a first metal layer as an electrode above the top surface of the first insulator;
- (d) forming a second insulator above the first metal layer;
- (e) forming a second area in the second insulator;
- (f) forming a second metal layer in the second area;
- (g) forming a third insulator above the second metal layer;
- (h) forming a third area in the third insulator;
- (i) forming a first dielectric in the third area;
- and
- (j) forming a third metal layer over at least a portion of the first dielectric.
8 more elements
A process for fabricating a planarized interleaved capacitor comprising the steps of:
- (a) disposing a first insulator;
- (b) planarizing the first insulator;
- (c) forming a first area in the first insulator;
- (d) disposing a first metal layer as an electrode in the first area;
- (e) planarizing the first metal layer and the first insulator;
- (f) disposing a second insulator above the first metal layer;
- (g) forming a second area in the second insulator;
- (h) forming a second metal layer in the second area;
- (i) planarizing the second metal layer and the second insulator;
- (j) forming a third insulator above the second metal layer;
- (k) forming a third area in the third insulator;
- (l) forming a first dielectric in the third area;
- (m) planarizing the first dielectric;
- and
- (n) forming a third metal layer over at least a portion of the first dielectric.
12 more elements
Dependencies are inferred from the claim text.