Scalable high-voltage devices

A method of fabricating a semiconductor device comprising:

• forming a trench on the face of a silicon substrate of a first conductivity type;
• forming a barrier layer over the substrate;
• depositing a conformal silicon layer of a second conductivity type into the trench;
• etching away the silicon layer of a second conductivity type selectively to leave remaining shoulder portions of the silicon layer in comers of the trench;
• annealing to drive dopant from the remaining portions of the silicon layer through walls of the trench into adjacent areas of the silicon substrate;
• removing the remaining portions of silicon from the trench;
• and,
• forming a gate structure in the trench and source and drain diffusion regions in said silicon substrate on opposing sides of said gate structure.

A semiconductor device comprising:

• a silicon substrate doped to be a first conductivity type;
• a conductive gate structure extending into said substrate and electrically isolated from said substrate by a dielectric barrier layer;
• diffusion regions doped to be a second conductivity type located at the surface of said substrate on opposing sides of said gate structure;
• and
• conduction enhancement regions doped to be a second conductivity type in said substrate abutting the dielectric layer and below the level of the diffusion regions, said conduction enhancement regions further comprising pockets adjacent to bottom comers of the gate structure.