US 6,333,226 B1Granted

Method of manufacturing semiconductor memory device having a capacitor

AssigneeOki Electric Industry Co., Ltd.

InventorsMasahiro Yoshida, Hideyuki Ando

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Abstract

Disclosed herein is a semiconductor memory device. In the semiconductor memory device, a transfer transistor having a drain region and a source region is formed on an Si semiconductor substrate. A lower end of a storage node is electrically connected to the drain region through a drain contact hole defined in an interlayer insulator. The storage node has an on-film extending portion which extends on an upper surface of the interlayer insulator, and a fin-shaped electrode portion which protrudes from the on-film extending portion. Structurally, the fin-shaped electrode portion is provided within a capacitor region so as to extend within a region smaller than the capacitor region and is spaced away from the on-film extending portion on the side of a bit line contact hole defined in the interlayer insulator.

Claims34

Dependent claims

A method of manufacturing a semiconductor memory device, comprising:

forming a transistor having a first conductive layer, a second conductive layer and a gate electrode on a semiconductor substrate;
forming a first insulating film and a stopper insulating film on said transistor;
forming a first opening in said first insulating film and said stopper insulating film so as to expose a portion of said first conductive layer;
forming a first conductive film serving as a first electrode over a range from a portion of an exposed surface of said stopper insulating film to said first conductive layer exposed in said first opening;
forming a sacrifice film on said first conductive film;
forming a second conductive film serving as said first electrode on said sacrifice film;
removing said sacrifice film;
forming a second insulating film so as to cover exposed portions of said first and second conductive films;
forming a third conductive film serving as a second electrode on said second insulating film;
forming a second opening in said insulating film and said stopper insulating film so as to expose a portion of said second conductive layer;
and
embedding a conductive substance in said second opening so that a height from the second conductive layer to a top of the conductive substance is higher than a height from the first conductive layer to a top of the stopper insulating film and lower than a height from the first conductive layer to a top of the third conductive film.

9 more elements

A method of forming a capacitor structure suitable for use in a semiconductor memory device wherein a storage node constituting a capacitor is connected to a first conductive layer through a first opening formed through an insulating film and a bit line is connected to a second conductive layer through a second opening formed through the insulating film, the method comprising:

forming said insulating film and a stopper film on a semiconductor substrate with the first and second conductive layers formed thereon;
forming the first opening above said first conductive layer through said insulating film and said stopper film;
forming a first storage node material film over an upper surface of said stopper film and said first conductive layer exposed from the first opening;
forming a sacrifice film on an upper surface of said first storage node material film;
patterning said sacrifice film and said first storage node material film;
covering said patterned sacrifice film and first storage node material film with a second storage node material film;
patterning said second storage node material film so as to expose said sacrifice film;
removing said sacrifice film;
forming a dielectric film on the surfaces of said first and second storage node material films;
forming a cell plate material film on said dielectric film;
and
forming a bit line on the second opening so that a height from the second conductive layer to a top of the bit line is higher than a height from the first conductive layer to a top of the stopper film and lower than a height from the first conductive layer to a top of the cell plate material film.

9 more elements

Dependencies are inferred from the claim text.