Method for improving planarization of an ILD layer
AssigneeUnited Microelectronics Corp.
InventorChiu-Te Lee
Life of this patent
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Abstract
An improved embedded DRAM fabricating process is disclosed. The method includes first forming a first dielectric layer on the surface of a semiconductor wafer covering a memory region and a logic region that are previously defined on the semiconductor wafer, forming a conductive layer over the first dielectric layer, forming at least one dummy pattern over the logic region and a plurality of storage nodes over the memory region in the conductive layer, forming an insulating layer and a top electrode on each of the storage nodes, and forming a second dielectric layer on the surface of the semiconductor wafer that covers the top electrode and the dummy pattern. The second dielectric layer fills the spaces between the dummy pattern.
Claims18
A method for improving planarization of an inter layer dielectric (ILD) layer, the method comprising:
- providing a semiconductor wafer, at least one memory cell and one periphery area being defined on the surface of the semiconductor wafer;
- forming a first dielectric layer on the surface of the semiconductor wafer covering the memory cell area and the periphery area;
- forming a silicon layer over the first dielectric layer;
- forming at least one dummy pattern over the periphery area and a plurality of storage nodes over the memory cell area in the silicon layer;
- forming an insulating layer and a top electrode on each of the storage nodes;
- and
- forming a second dielectric layer on the surface of the semiconductor wafer that covers the top electrode and the dummy pattern.
A method for improving planarization of an inter layer dielectric (ILD) layer during an embedded DRAM manufacturing process, the method comprising:
- providing a semiconductor wafer, at least one memory cell and one periphery area being defined on the surface of the semiconductor wafer;
- forming an AP oxide layer on the semiconductor wafer that covers the memory cell area and the periphery area;
- forming a silicon layer over the AP oxide layer;
- performing a lithographic process and an etching process to simultaneously form at least one dummy pattern and a plurality of storage nodes over the periphery area and memory cell area respectively in the silicon layer;
- forming an insulating layer and a top electrode on each of the storage nodes;
- performing an etch back process to create a sharp structure on the dummy pattern and simultaneously defining the top electrode;
- and
- forming a dielectric layer on the surface of the semiconductor wafer that covers the top electrode and the dummy pattern, the dielectric layer filling a spacing between the dummy pattern;
- wherein the width of the spacing between the dummy pattern is less than half the thickness of the dielectric layer.
Dependencies are inferred from the claim text.