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US 6,324,481 B1Granted
Method for the calculation of wafer probe yield limits from in-line defect monitor data
AssigneeTexas Instruments Incorporated
InventorsNick Atchison, Ron Ross
Life of this patent
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Abstract
A method of calculating yield limits for a factory to process semiconductor wafers, including the steps of generating a wafer map from the semiconductor wafers, eliminating die on said wafer map from consideration that have multiple defects, calculating killer probability for each of said die having only one defect, and predicting yield limits from said killer probabilities.
Claims1
A method of calculating yield limits for a factory to process semiconductor wafers, comprising the steps of:
- generating a wafer map from the semiconductor wafers;
- eliminating die on said wafer map from consideration that have multiple defects;
- calculating killer probability for each of said die having only one defect;
- and
- predicting yield limits from said killer probabilities.
2 more elements
Dependencies are inferred from the claim text.