US 6,323,709 B1 · High-speed, compact, edge-triggered, flip-flop circuit

Abstract

A high-speed, compact, edge-triggered flip-flop circuit is provided which includes an input circuit section, a latch circuit section and an output circuit section. The input circuit section includes at least one transistor such as a field-effect transistor (FET) which determines the logic function of the flip-flop such as D, S-R, or T, and provides a first stage of latching. The input circuit section receives the logic control signals such as D, S-R, or T, and a clock signal. In one embodiment of the invention, the latch circuit section includes two series-connected negative differential resistance (NDR) diodes. In this embodiment, a common terminal of the two NDR diodes is connected to the data output of the input circuit section and to the data input of the output circuit section. In the first embodiment, the output circuit section includes a plurality of FETs which perform second stage of latching such that the output of this section reflects the logic of the chosen inputs only at the occurrence of either a low-to-high transition or a high-to-low transition on the clock signal, but not both, depending on the chosen configuration of the flip-flop circuit. In a second embodiment, a D flip-flop circuit includes a latch circuit section which includes at least one NDR diode connected to the data output of the input circuit section and an output circuit section which also includes at least one NDR diode connected to the output of the output circuit section. In the second embodiment, the flip-flop circuit may use: 1) bistable NDR logic; 2) cascaded NDR latches; or 3) pseudo-bistable NDR logic with a true, single-phase clock.

Claims33

Dependent claims

A high-speed, compact, edge-triggered, flip-flop circuit comprising:

an input circuit section having at least one input for receiving at least one input signal, a clock input for receiving a clock signal having two states and a data output;
a latch circuit section having at least one semiconductor device, the at least one semiconductor device having negative differential resistance characteristics and being connected to the data output of the input circuit section;
and
an output circuit section having a data input connected to the at least one semiconductor device, a clock input for receiving the clock signal and a data output wherein a value is stored at the data output of the output circuit section in response to the at least one input signal when the clock signal makes a transition from one of its states to the other one of its states.

1 more element

A flip-flop circuit including a clock input, data input, and a Q output comprising:

an input block including a first input coupled to the data input, a second input coupled to the clock input, and an output, said input block for coupling said data input to the said output when the clock signal applied to the clock input is in a first phase;
a latch circuit including a common terminal coupled to said output of said input block and also to a first input of an output block, said latch circuit for storing the value of the said output of the said input block;
and
said output block including a first input coupled to the said common terminal of the said latch circuit, a second input coupled to the clock input, and an output coupled to the Q output, said output block for receiving the data from the said latch circuit and storing it at the said Q output when the clock signal applied to the clock input transitions from a first phase to a second phase.

1 more element

Dependencies are inferred from the claim text.

High-speed, compact, edge-triggered, flip-flop circuit

Life of this patent

High-speed, compact, edge-triggered, flip-flop circuit

Life of this patent

Abstract

Claims33