Insertion of spare logic gates into the unused spaces between individual gates in standard cell artwork
AssigneeAgilent Technologies, Inc.
InventorHarold H. Yount, Jr.
Life of this patent
Estimating the term…
Abstract
Apparatus for placing and routing an integrated circuit, the apparatus comprising one or more computer readable storage media. Computer readable program code is stored in the one or more computer readable storage media. The computer readable code comprises code for placing a plurality of logic cells in the integrated circuit and code for placing one or more spacer cells in the integrated circuit to fill one or more empty spaces between the plurality of logic cells. The one or more spacer cells comprise a spare logic gate.
Claims22
A method for designing an integrated circuit having spare logic gates, comprising:
- placing a plurality of logic cells on an area of said integrated circuit;
- placing a plurality of spacer cells among said plurality of logic cells to fill a plurality of empty spaces between said plurality of logic cells;
- and
- routing a plurality of electrical connections among said plurality of logic cells and said plurality of spacer cells to form said integrated circuit.
A method of manufacturing an integrated circuit, comprising:
- a. placing and routing a plurality of logic cells and a plurality of spacer cells in an integrated circuit design, said spacer cells comprising one or more spare logic gates configured in an inactive state;
- and
- b. fabricating one or more integrated circuits according to said integrated circuit design.
Apparatus for placing and routing an integrated circuit, the apparatus comprising:
- a. one or more computer readable storage media;
- and
- b. computer readable program code stored in the one or more computer readable storage media, the computer readable code comprising:
- i. code for placing a plurality of logic cells in said integrated circuit;
- and
- ii. code for placing one or more spacer cells in said integrated circuit to fill one or more empty spaces between said plurality of logic cells, wherein said one or more spacer cells comprise a spare logic gate.
An apparatus for designing an integrated circuit having spare logic gates, comprising:
- a means for placing a plurality of logic cells on an area of said integrated circuit;
- a means for placing a plurality of spacer cells among said plurality of logic cells to fill a plurality of empty spaces between said plurality of logic cells;
- and
- a means for routing a plurality of electrical connections among said plurality of logic cells and said plurality of spacer cells to form said integrated circuit.
An apparatus for designing an integrated circuit having spare logic gates, comprising:
- an assembly which places a plurality of logic cells on an area of said integrated circuit;
- an assembly which places a plurality of spacer cells among said plurality of logic cells to fill a plurality of empty spaces between said plurality of logic cells;
- an assembly which routes a plurality of electrical connections among said plurality of logic cells and said plurality of spacer cells to form said integrated circuit.
A computer data signal embodied in a transmission medium comprising computer source code defining one or more spacer cells to be placed in a design for an integrated circuit, said one or more spacer cells for filling one or more empty spaces in said design, wherein said one or more spacer cells comprise a spare logic gate.
Dependencies are inferred from the claim text.