Testable circuit with a low number of leads

A method of testing an electronic device which includes a microcontroller which can be set in a specific mode in which internal registers can be modified from outside, a peripheral internally coupled to the microcontroller via interface registers, a single input/output lead for communicating with the microcontroller from the outside, a peripheral input lead and a peripheral output lead, a microcontroller clock lead and a peripheral clock lead, wherein the interface registers can be connected according to a shift register configuration forming a test scan path accessible in series and clocked by a clock signal to be applied to the peripheral clock lead, and including a test aid circuit which, in a scan mode, connects the interface registers according to the shift register configuration, the scan mode being selected when a test bit, accessible through the input/output lead, is enabled, and when the input/output lead is forced from the outside to a state distinct from its default state, the method including the steps of:

• enabling the test bit via the input/output lead;
• stopping the clock of the microcontroller;
• forcing the input/output lead to the state opposite to its default state;
• and
• inputting or extracting data in series at the rate of the peripheral clock in the scan path through the input lead or through the output lead of the peripheral.