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US 6,320,780 B1Granted
Reduced impact from coupling noise in diagonal bitline architectures
AssigneeInfineon Technologies North America Corp.
InventorsGerhard Mueller, Ulrike Gruening
Life of this patent
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Abstract
An integrated circuit comprising first and second adjacent signal line pairs 310 and 320 is described. The signal line pairs comprise diagonal signal paths 311p, 312p; 321p and 322p with directional changes 335. The first signal line pair comprises m twists 340, where m is a whole number ≧1, and the second signal line pair comprises n twists 360 and 361, where n is a whole number ≠m.
Claims21
An integrated circuit comprising:
- a plurality of signal line pairs, wherein each pair occupies a diagonal signal path with directional changes;
- a plurality of twists in each of the signal line pairs, wherein adjacent signal line pairs have an unequal number of twists such that a first signal line pair has m twists, where m is a whole number ≧1 m, and an adjacent second signal line pair has n twists, where n is a whole number ≠m, the twists switch diagonal signal paths of a first and a second signal line of each signal pair respectively.
Dependencies are inferred from the claim text.