Methods and apparatus for a terminated fail-safe circuit
AssigneeTexas Instruments Incorporated
InventorsMark W. Morgan, Fernando D. Carvajal, Kevin J. Gingerich
Life of this patent
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Abstract
An active fail-safe method and apparatus for a LVDS receiver that uses a window comparator circuit to monitor the differential voltage at the receiver's input pins and drive the output to a known logic HIGH state in the absence of a valid input signal; i.e., when the input differential signal is less than a chosen threshold value of approximately 80 mV. Such a condition may occur when the cable is removed or damaged in such a way that no valid input signal is present. In the presence of a valid input signal, the circuit's output tracks the differential input without any degradation to the signal.
Claims21
An active fail-safe LVDS receiver circuit that provides a known logic level output in the absence of a differential in signal, comprising:
- a relatively high-speed main receiver having inputs coupled to a first and second differential input, and having an output;
- a window comparator also coupled to said first and second differential inputs consisting of first and second fail-safe comparators, each having a first and a second differential input, wherein the first input of said first fail-safe comparator is coupled to the second input of said fail-safe second comparator and to the second input of said main receiver and the second input of said fail-safe first comparator is coupled to the first input of said second fail-safe comparator and to the first input of said main receiver;
- a fail-safe activity timer coupled to the output of said main receiver;
- a logic gate having inputs coupled to the outputs of said first and second fail-safe comparators and to the output of said fail-safe timer;
- and
- an output buffer having inputs coupled to the output of said main receiver and to the output of said logic gate.
An active fail-safe method, which prevents an LVDS receiver from switching on input noise in the absence of an input signal, comprising the steps of:
- monitoring both differential inputs on a continuous basis using a window comparator, to detect a loss of input signal;
- if said inputs are within λmV of each other, driving said window comparator outputs HIGH and gating said window comparator outputs with the output of a 600 nSec fail-safe timer;
- and
- if said input signal is still absent after said timer expires, driving said LVDS receiver's output to a known logic HIGH state and holding said HIGH state until said input signal is restored.
A fail-safe circuit that provides a known logic level output in the absence of a differential input signal, comprising:
- a relatively high-speed receiver having inputs coupled to a first and second differential input, and having an output;
- a window comparator also coupled to said first and second differential inputs, comprising first and second comparators, each having a first and a second differential input, wherein the first input of said first comparator is coupled to the second input of said second comparator and to the second input of said receiver and the second input of said first comparator is coupled to the first input of said second comparator and to the first input of said receiver;
- a timer coupled to the output of said receiver;
- a logic circuit having inputs coupled to the outputs of said first and second comparators and to the output of said timer, providing an active output only when all inputs are active;
- and
- an output buffer having inputs coupled to the output of said receiver and to the output of said logic circuit, such that said output buffer provides an output corresponding to the output of said receiver when the output of said logic circuit is inactive, and provides an output having a predetermined logic state when said logic circuit is active.
Dependencies are inferred from the claim text.