CMOS semiconductor device

A CMOS semiconductor device, comprising:

• a semiconductor substrate of a first conductivity type;
• a well region of a second conductivity type formed selectively in a surface region of said semiconductor substrate;
• a first shallow well region of the second conductivity type formed selectively in a surface region of said well region in a manner to partly overlap with the well region;
• a source region and a drain region of a first MOS transistor, said source and drain regions made of diffusion regions of the first conductivity type formed selectively in a surface region of the first shallow well region;
• a first gate electrode formed above a channel region between the source region and drain region of the first MOS transistor with a gate insulating film interposed therebetween;
• a second shallow well region of the second conductivity type formed selectively in a surface region of the well region;
• a first shallow well leading region made of a diffusion region of the second conductivity type formed selectively in a surface region of the second shallow well region;
• first shallow trench isolating regions formed in a surface region of the well region and positioned between the source region of the first MOS transistor and the first shallow well leading region and between the first shallow well region and the second shallow well region, said first shallow trench isolating regions being formed deeper than the first shallow well region and the second shallow well region;
• a third shallow well region of the first conductivity type formed selectively in a surface region of the semiconductor substrate;
• a fourth shallow well region of the first conductivity type formed selectively in a surface region of the semiconductor substrate;
• a source region and a drain region of a second MOS transistor, said source and drain regions made of diffusion regions of the second conductivity type formed selectively in a surface region of the third shallow well region;
• a second gate electrode formed above a channel region between the source region and the drain region of the second MOS transistor with a gate insulating film interposed therebetween;
• a second shallow well leading region made of a diffusion region of the first conductivity type formed selectively in a surface region of the fourth shallow well region;
• second shallow trench isolating regions formed in a surface region of the semiconductor substrate and positioned between the source region of the second MOS transistor and the second shallow well leading region and between the third shallow well region and the fourth shallow well region, said second shallow trench isolating regions being formed deeper than the third shallow well region and the fourth shallow well region;
• third shallow trench isolating regions formed in a surface region of the semiconductor substrate and positioned between the drain region of the first MOS transistor and the drain region of the second MOS transistor and between the first shallow well region and the third shallow well region, said third shallow trench isolating regions being formed deeper than the first shallow well region and the third shallow well region;
• and
• fourth shallow trench isolating regions for isolating CMOS regions, said fourth shallow trench isolating regions being formed in a surface region of the semiconductor substrate for isolating another element region from the first shallow well leading region and for isolating still another element region from the second shallow well leading region.