US 6,320,217 B1Granted

Semiconductor memory device

AssigneeMatsushita Electric Industrial Co., Ltd.

InventorsMasanori Tagami, Fumihiko Noro

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Abstract

Conventionally, an insulating film for element isolation has had a uniformly large thickness either in a memory cell area and in a peripheral circuit area so that the total film thickness of the memory cell area having a floating gate electrode, a control gate electrode, and an erase gate electrode is extremely increased, resulting in a large height difference between the memory cell area and the peripheral circuit area. The insulating film for element isolation in the peripheral circuit area should be thick, while the insulating films for element isolation in the memory cell area need not be as thick as the insulating film for element isolation in the peripheral circuit area in terms of operation. Therefore, the total film thickness of the memory cell area as well as the height difference between the memory cell area and the peripheral circuit area can be reduced by forming the insulating films for element isolation in the memory cell area which are thinner than the insulating film for element isolation in the peripheral circuit area.

Claims2

Dependent claims

A semiconductor memory device having a memory cell area and a peripheral circuit area each provided in a semiconductor substrate, said device comprising:

source and drain regions formed in specified regions of the semiconductor substrate located in said memory cell area;
an insulating film for element isolation in the peripheral circuit area formed on top of and non-recessed in a main surface of the semiconductor substrate and in a specified region of the semiconductor substrate located in said peripheral circuit area;
a pair of insulating films for element isolation in the memory cell area formed on top of and non-recessed in a main surface of the semiconductor substrate and in specified regions of the semiconductor substrate located in said memory cell area, each of said pair of insulating films for element isolation in the memory cell area having a thickness smaller than that of said insulating film for element isolation in the peripheral circuit area;
a gate insulating film formed on a portion of said semiconductor substrate isolated by said pair of insulating films for element isolation in the memory cell area;
a floating gate electrode formed in contact with an end portion of at least one of said pair of insulating films for element isolation in the memory cell area in a specified region located between said source and drain regions and over said gate insulating film;
a control gate electrode formed above said floating gate electrode;
and
an erase gate electrode formed on said one of the insulating films for element isolation in the memory cell area formed with said floating gate electrode, said erase gate electrode being in contact with a sidewall of said floating gate electrode via a tunneling insulating film and with said control gate electrode via an interlayer insulating film.

5 more elements

Dependencies are inferred from the claim text.