Hetero-junction field effect transistor

A hetero-junction field effect transistor comprising:

• (a) a first semiconductor layer composed of InP;
• (b) a second semiconductor layer formed on said first semiconductor layer, said second semiconductor layer having a smaller electron affinity than that of said first semiconductor layer;
• (c) a third semiconductor layer formed on said second semiconductor layer, said third semiconductor layer having a greater electron affinity than that of said second semiconductor layer, and being formed at a surface thereof with an opening, said third semiconductor layer being) composed of InP;
• (d) source and drain electrodes formed on said third semiconductor layer;
• and
• (e) a gate electrode formed on said second semiconductor layer in said opening of said third semiconductor layer, wherein said first semiconductor layer is comprised of an n-type semiconductor layer.

A hetero-junction field effect transistor comprising:

• (a) a first semiconductor layer composed of InP;
• (b) a second semiconductor layer formed on and contiguous to said first semiconductor layer, said second semiconductor layer having a smaller electron affinity than that of said first semiconductor layer;
• (c) a third semiconductor layer formed on said second semiconductor layer, said third semiconductor layer having a greater electron affinity than that of said second semiconductor layer, and being formed at a surface thereof with an opening, said third semiconductor layer being composed of InP;
• (d) source and drain electrode formed on said third semiconductor layer;
• and
• (e) a gate electrode formed on said second semiconductor layer in said opening of said third semiconductor layer, wherein said second semiconductor layer is composed of InAlAs.

A hetero-junction field effect transistor comprising:

• (a) a first semiconductor layer composed of InP;
• (b) a second semiconductor layer formed on and contiguous to said first semiconductor layer, said second semiconductor layer having a smaller electron affinity than that of said first semiconductor layer;
• (c) a third semiconductor layer formed on said second semiconductor layer, said third semiconductor layer having a greater electron affinity than that of said second semiconductor layer, and being formed at a surface thereof with an opening, said third semiconductor layer being composed of InP;
• (d) source and drain electrode formed on said third semiconductor layer;
• and
• (e) a gate electrode formed on said second semiconductor layer in said opening of said third semiconductor layer, wherein said second semiconductor layer is comprised of an n-type InAlAs semiconductor layer.

A hetero-junction field effect transistor comprising:

• (a) a first semiconductor layer composed of InP;
• (b) a second semiconductor layer formed on said first semiconductor layer, said second semiconductor layer having a smaller electron affinity than that of said first semiconductor layer;
• (c) a third semiconductor layer formed on said second semiconductor layer, said third semiconductor layer having a greater electron affinity than that of said second semiconductor layer, and being formed at a surface thereof with an opening, said third semiconductor layer being composed of InP;
• (d) source and drain electrode formed on said third semiconductor layer;
• and
• (e) a gate electrode formed on said second semiconductor layer in said opening of said third semiconductor layer, wherein said second semiconductor layer is comprised of a plurality of n-type semiconductor layers.

A hetero-junction field effect transistor comprising:

• (a) a first semiconductor layer composed of InP;
• (b) a second semiconductor layer formed on said first semiconductor layer, said second semiconductor layer having a smaller electron affinity than that of said first semiconductor layer;
• (c) a third semiconductor layer formed on said second semiconductor layer, said third semiconductor layer having a greater electron affinity than that of said second semiconductor layer, and being formed at a surface thereof with an opening, said third semiconductor layer being composed of InP;
• (d) source and drain electrodes formed on said third semiconductor layer;
• and
• (e) a gate electrode formed on said second semiconductor layer in said opening of said third semiconductor layer,
• wherein said second semiconductor layer is composed of InAlAs, further comprising a fourth semiconductor layer sandwiched between said second and third semiconductor layers, said fourth semiconductor layer being composed of InAlGaAs.

A hetero-junction field effect transistor comprising:

• (a) a first semiconductor layer composed of InP;
• (b) a second semiconductor layer formed on said first semiconductor layer, said second semiconductor layer having a smaller electron affinity than that of said first semiconductor layer;
• (c) a third semiconductor layer formed on said second semiconductor layer, said third semiconductor layer having a greater electron affinity than that of said second semiconductor layer, and being formed at a surface thereof with an opening, said third semiconductor layer being composed of InP;
• (d) source and drain electrodes formed on said third semiconductor layer;
• and
• (e) a gate electrode formed on said second semiconductor layer in said opening of said third semiconductor layer, further comprising a fifth semiconductor layer sandwiched between said third semiconductor layer and said source and drain electrodes, said fifth semiconductor layer being composed of n-type InGaAs.

A hetero-junction field effect transistor comprising:

• (a) a first semiconductor layer composed of InP;
• (b) a second semiconductor layer formed on and contiguous to said first semiconductor layer, said second semiconductor layer having a smaller electron affinity than that of said first semiconductor layer;
• (c) a third semiconductor layer formed on said second semiconductor layer, said third semiconductor layer having a greater electron affinity than that of said second semiconductor layer, and being formed at a surface thereof with an opening, said third semiconductor layer being composed of InP;
• (d) source and drain electrode formed on said third semiconductor layer;
• and
• (e) a gate electrode formed on said second semiconductor layer in said opening of said third semiconductor layer, wherein said second semiconductor layer is formed with a recess in alignment with said opening of said third semiconductor layer, and wherein said gate electrode is formed on said second semiconductor layer in said recess.

A hetero-junction field effect transistor comprising:

• (a) a first semiconductor layer;
• (b) a second semiconductor layer formed on and contiguous to said first semiconductor layer, said second semiconductor layer having a smaller electron affinity than that of said first semiconductor layer;
• and,
• (c) a third semiconductor layer formed on said second semiconductor layer, said third semiconductor layer having a greater electron affinity than that of said second semiconductor layer, and being formed at a surface thereof with an opening.
• wherein the conduction band offset between said first layer and said second layer is approximately equal to the conduction band offset between said second layer and said third layer.