For mol integration
AssigneeInternational Business Machines Corporation
InventorsGregory Costrini, Mihel Seitz
Life of this patent
Estimating the term…
Abstract
A method of fabricating a semiconductor device in which the bitlines and the bitline contacts are fabricated utilizing a single masking step in which line-space resist patterns are employed in defining the regions for the bitlines and the bitline contacts. The method utilizes a first line-space resist pattern and a second line-space resist pattern which is perpendicularly aligned to the first line-space resist pattern to form bitlines that are self-aligned to the bitline contacts.
Claims17
A method of forming a semiconductor device including MOSFETs, bitlines and bitline contacts, wherein said bitline contacts are self-aligned to said bitlines, said method comprising the steps of:
- (a) providing a semiconductor structure having a plurality of patterned gate conductors formed on a surface of a gate dielectric, each of said patterned gate conductors including sidewall spacers formed thereon and being separated by a gap region, said gap region being filled with a dielectric material;
- (b) forming an oxide cap layer on said dielectric material;
- (c) forming a hard mask on said oxide cap layer;
- (d) forming a first photoresist on said hard mask, said first photoresist having a first line-space pattern formed therein;
- (e) etching through said first line-space pattern so as to pattern the hard mask and to partially remove said oxide cap layer;
- (f) forming a second photoresist on said patterned hard mask, said second photoresist having a second line-space pattern formed therein which is perpendicular to said first line-space pattern, whereby a portion of said oxide cap layer between said first and second line-space patterns is exposed;
- (g) etching through said exposed portion of said oxide cap layer so as to provide an opening to said gate dielectric in a device contact region;
- (h) filling said opening with polysilicon;
- (i) etching said polysilicon below a top surface of said oxide cap layer so as to form a recessed area in said opening;
- and
- (j) forming a bitline so as to contact said recessed area provided in step (i).
Dependencies are inferred from the claim text.