Technique for reducing dishing in Cu-based interconnects
AssigneeAgere Systems Guardian Corp.
InventorsSailesh Chittipeddi, Sailesh Mansinh Merchant, Pradip Kumar Roy
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Abstract
The present invention includes a method for reducing dishing of an integrated circuit interconnect, comprising the steps of providing excess interconnect material above a damascene feature in a substrate and planarizing the substrate and interconnect material to obtain an interconnect in the substrate.
Claims19
A method for reducing dishing of an integrated circuit interconnect, comprising the steps of:
- depositing an electrically conductive interconnect material onto a substrate comprised of a substrate material, and wherein the substrate comprises a damascene feature;
- planarizing the interconnect material and substrate until an interconnect exhibits dishing;
- depositing and curing photoresist;
- planarizing to provide cured resist in the interconnect dish;
- partially etching the substrate, wherein the etching is selective for the substrate material;
- and
- planarizing the interconnect material, photoresist and substrate.
A method for reducing dishing of an integrated circuit interconnect, comprising the steps of:
- depositing an electrically conductive interconnect material onto a substrate comprised of a substrate material, and wherein the substrate comprises a damascene feature;
- depositing photoresist and patterning the photoresist to provide cured resist over the damascene feature;
- etching the interconnect material, wherein the etching is selective for the interconnect material;
- and
- planarizing the interconnect material, photoresist and substrate to provide an interconnect in the substrate.
A method for reducing dishing of an integrated circuit interconnect, comprising the steps of:
- depositing an electrically conductive interconnect material onto a substrate comprised of a substrate material, and wherein the substrate comprises a damascene feature, and wherein the substrate material is more abrasion resistant than the interconnect material, and wherein the interconnect material is selected from the group consisting of copper and copper alloys;
- depositing photoresist and patterning the photoresist to provide cured resist over the damascene feature;
- etching the interconnect material, wherein the etching is selective for the interconnect material;
- and
- chemical mechanical polishing the interconnect material, photoresist and substrate to provide an interconnect in the substrate.
A method for reducing dishing of an integrated circuit interconnect, comprising the steps of;
- providing excess interconnect material above a damascene feature in a substrate;
- and
- planarizing the substrate and interconnect material to obtain an interconnect in the substrate.
Dependencies are inferred from the claim text.