Pattern factor checkerboard for planarization
AssigneeInternational Business Machines Corporation
InventorAnthony K. Stamper
Life of this patent
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Abstract
A method of fabricating a semiconductor device on a semiconductor wafer of the type having a plurality of active layers that includes the steps forming a layout for at least one of the active layers where the layout contains a plurality of active region segments and a plurality of inactive regions. The layout is then modified by adding a plurality of dummy active segments in the inactive regions. The layout is further modified by removing a plurality of sub-regions from the active regions to form a plurality of sub-inactive regions. The semiconductor wafer is then processed using the modified layout to provide an environment during the processing of the active layer wherein the relative area of the active to the inactive regions is substantially equal across the wafer.
Claims17
A method of fabricating a semiconductor device having a plurality of active layers, comprising:
- forming a layout for at least one active layer comprising a plurality of active region segments and a plurality of inactive regions;
- modifying said layout by removing a plurality of sub-regions from said active regions to form a plurality of sub-inactive regions;
- and
- processing a semiconductor wafer using said modified layout to provide an environment during the processing of said active layer wherein the relative area of active to inactive regions is substantially equal across said wafer.
Dependencies are inferred from the claim text.