Method to reduce via poison in low-k Cu dual damascene by UV-treatment
AssigneeTaiwan Semiconductor Manfacturing Company, Ltd.
InventorsWeng Chang, Lain-Jong Li, Shwang Ming Jeng, Syun-Ming Jang
Life of this patent
Estimating the term…
Loading patent…
AssigneeTaiwan Semiconductor Manfacturing Company, Ltd.
InventorsWeng Chang, Lain-Jong Li, Shwang Ming Jeng, Syun-Ming Jang
Estimating the term…
A method to reduce via poisoning in low-k copper dual damascene interconnects through ultraviolet (UV) irradiation of the damascene structure is disclosed. This is accomplished by irradiating the insulative layers each time the layers are etched to form a portion of the damascene structure. Thus, irradiation is performed once after the forming of a trench or a via, and again for the second time when the insulative layers are etched to form the remaining trench or via. The trench and hole openings of the dual damascene structure are exposed to UV light in a dry ozone environment, which then favorably alters the surface characteristics of the low-k dielectric walls which are normally hydrophobic. Hence, during etching, moisture is not absorbed into the walls. Furthermore, it is found that the UV treatment inhibits reaction between the walls and the photoresist used during the forming of the damascene structure, thereby providing clean openings without any photoresist residue, and hence, much less poisoned contacts/vias. Consequently, as copper is deposited into the clean damascene, voids are avoided, and a Cu dual damascene interconnect with low RC delay characteristics is obtained.
A method to reduce via poison in low-k Cu dual damascene by UV-treatment comprising the steps of:
A method to reduce via poison in low-k Cu dual damascene by UV-treatment comprising the steps of:
Dependencies are inferred from the claim text.