Semiconductor device manufacturing method and semiconductor wafer
AssigneeNEC Corporation
InventorHidetoshi Sumitani
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Abstract
In a method of manufacturing a semiconductor device, a first chip region and a second chip region are provided on a silicon wafer. A first resist pattern for the semiconductor device is to be formed in the first chip region, and the second chip region includes a plurality of characteristic evaluation regions for the semiconductor device, and a second resist pattern is to be formed in each of the plurality of characteristic evaluation regions for the semiconductor device. A data rate of the second chip region is determined based on a data rate of the first chip region. The data rate of the second chip region is determined such that a ratio of the data rate of the first chip region to the data rate of the second chip region is in a range of ¼ to 4.
Claims20
A method of manufacturing a semiconductor device, comprising the steps of:
- providing a product chip region and a TEG chip region on a silicon wafer, wherein said TEG chip region includes a plurality of characteristic evaluation regions for said semiconductor device;
- forming a first resist pattern for said semiconductor device to be formed in said product chip region;
- forming a second resist pattern in said TEG chip region, in each of said plurality of characteristic evaluation regions for said semiconductor device;
- and
- determining a data rate of said TEG chip region based on a data rate of said product chip region.
A method of manufacturing a semiconductor device for storing a program in a recording medium, comprising the steps of:
- providing a product chip region and a TEG chip region on a silicon wafer, wherein said TEG chip region includes a plurality of characteristic evaluation regions for said semiconductor device;
- forming a first resist pattern for said semiconductor device to be formed in said product chip region;
- forming a second resist pattern in said TEG chip region, in each of said plurality of characteristic evaluation regions for said semiconductor device;
- and
- determining a data rate of said TEG chip region based on a data rate of said product chip region.
A semiconductor wafer comprising:
- a product chip region;
- a TEG chip region;
- a first resist pattern for a semiconductor device formed in said product chip region;
- a plurality of characteristic evaluation regions for said semiconductor device in said TEG chip region;
- and
- a second resist pattern formed in said TEG chip region, in each of said plurality of characteristic evaluation regions for said semiconductor device,
- wherein each of said plurality of characteristic evaluation regions includes a first region and a second region, and a test pattern for characteristic test of said semiconductor device formed in said product chip region.
Dependencies are inferred from the claim text.