Using high temperature H2 anneal to recrystallize S/D and remove native oxide simultaneously

A method of fabricating silicided gate, source and drain regions in the fabrication of an integrated circuit device comprising:

• providing semiconductor device structures in and on a semiconductor substrate Wherein said semiconductor device structures include gate electrodes and associated said source and drain regions;
• depositing a resist protective dielectric layer overlying said semiconductor device structures;
• etching away said resist protective dielectric layer where it is not covered by a mask exposing a top surface of said gate electrode and exposing a surface of said semiconductor substrate overlying said source and drain regions wherein a native oxide layer having a thickness of between 9 and 15 Angstrom forum on said exposed surfaces;
• thereafter depositing a metal layer overlying said resist protective oxide layer, said surface of said gate electrode, and said posed surface of said semiconductor substrate wherein, in-situ with said depositing of said metal layer, said substrate to annealed using H2whereby said native oxide thickness is reduced to between 3.5 and 7.3 Angstrom and whereby said exposed surface of said semiconductor substrate is recrystallized simultaneously;
• annealing said metal layer wherein said metal layer reacts with said underlying gate electrode and said semiconductor substrate where it is not covered by said resist protective dielectric layer to form a metal silicide layer;
• removing said metal layer that has not been transformed to said metal silicide layer leaving said metal silicide layer overlying said gate electrode and said source and drain regions to complete fabrication of said silicided gate, source and drain regions in the fabrication of said integrated circuit device.

A method of fabricating silicided gate, source and drain regions in the fabrication of an integrated circuit device comprising:

• providing semiconductor device structures in and on a semiconductor substrate wherein said semiconductor device structures include gate electrodes and associated said source and drain regions;
• depositing a resist protective dielectric layer overlying said semiconductor device structures;
• etching away said resist protective dielectric layer where it is not covered by a mask exposing a top surface of said gate electrode and exposing a surface of said semiconductor substrate overlying said source and drain regions wherein a native oxide layer forms having a thickness of between 9 and 15 Angstrom on said exposed surfaces;
• thereafter depositing a metal layer overlying said resist protective dielectric layer, said exposed surface of said gate electrode, and said exposed surface of said semiconductor substrate wherein, in-situ with said depositing of said metal layer, said substrate is annealed using H2at a high temperature of 800 to 1150 ° C. and at a low pressure of 6 to 100 Torr whereby said native oxide thickness is reduced to between 3.5 and 7.3 Angstroms and whereby said exposed surface of said semiconductor substrate is recrystallized simultaneously;
• annealing said metal layer wherein said metal layer reacts with said underlying gate electrode and semiconductor substrate where it is not covered by said resist protective dielectric layer to form a metal silicide layer;
• removing said metal layer that has not been transformed to said metal silicide layer leaving said metal silicide layer overlying said gate electrode and said source and drain regions to complete fabrication of said silicided gate, source and drain regions in the fabrication of said integrated circuit device.