Method of fabricating self-aligned multilevel mask ROM
AssigneeMacronix International Co., Ltd.
InventorsChung Yeh Lee, Pei-Ren Jeng
Life of this patent
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Abstract
A method of fabricating self-aligned multilevel mask read only memory (ROM). The method can improve the process window to reduce process difficulty by utilizing the self-aligned implantation. Moreover, by utilizing the height difference between different gate polysilicon layers and implantation of the ROM code with self-aligned implatiation to increase the difference between the threshold voltages of different gates, and therefore, multilevel cell transistors with for the mask ROM with multilevel threshold voltages are formed to times the capacity of the mask ROM.
Claims23
A method of fabricating a mask read only memory (ROM), comprising:
- forming a gate oxide layer and a polysilicon layer in sequence on a substrate;
- defining the polysilicon layer;
- performing a doping process to form a buried bit line in the substrate by using the polysilicon layer as a mask;
- defining the polysilicon layer to form a plurality of gate layers;
- forming a plurality of gate spacers around and on the sidewall of the gate layers;
- forming a silicon oxide layer over the substrate;
- removing a portion of the silicon oxide layer until exposing the top of the polysilicon layer;
- forming a first patterned photoresist layer on the substrate to cover parts of the polysilicon layer;
- removing a portion of the exposed polysilicon layer by using the first patterned photoresist layer as a mask;
- performing a first ion implantation process to form a first doped region in the substrate under the exposed polysilicon layer by using the first patterned photresist layer as a mask;
- removing the first patterned photoresist layer;
- forming a second patterned photoresist layer on the substrate to cover parts of the polysilicon layer;
- removing a portion of the exposed polysilicon layer by using the second patterned photoresist layer as a mask;
- performing a second ion implantation process to form a second doped region in the substrate under the exposed polysilicon layer by using the second patterned photoresist layer as a mask;
- removing the second patterned photoresist layer;
- and
- forming a conductive layer on the substrate to electrically connect to the exposed polysilicon layer.
A method of fabricating a mask read only memory (ROM), comprising:
- forming a gate oxide layer and a gate conductive layer in sequence on a substrate;
- defining the gate conductive layer;
- performing a doping process to form a buried bit line in the substrate by using the gate conductive layer as a mask;
- defining the gate conductive layer to form a plurality of gate layers;
- forming a plurality of gate spacers around and on the sidewall of the gate layers;
- forming an insulating layer over the substrate;
- removing a portion of the insulating layer until exposing the top of the gate conductive layer;
- forming a first patterned photoresist layer on the substrate to cover parts of the gate conductive layer;
- removing a portion of the exposed gate conductive layer by using the first patterned photoresist layer as a mask;
- performing a first doping process to form a first doped region in the substrate under the exposed gate conductive layer by using the first patterned photoresist layer as a mask;
- removing the first patterned photoresist layer;
- forming a second patterned photoresist layer on the substrate to cover parts of the gate conductive layer;
- removing a portion of the exposed gate conductive layer by using the second patterned photoresist layer as a mask;
- performing a second doping process to form a second doped region in the substrate under the exposed gate conductive layer by using the second patterned photoresist layer as a mask;
- removing the second patterned photoresist layer;
- and
- forming a conductive layer on the substrate to electrically connect to the exposed gate conductive layer.
Dependencies are inferred from the claim text.