Process for the fabrication of an integrated circuit comprising MOS transistors for low voltage, EPROM cells and MOS transistors for high voltage

A process for forming an integrated circuit comprising at least one low voltage transistor, at least one high voltage transistor, and at least one memory cell, the process comprising:

• a) forming a body region in at least one low voltage transistor area in a substrate, a body region in at least one high voltage transistor area in the substrate, and a body region in at least one memory cell area in the substrate;
• b) forming a first dielectric layer on the substrate;
• c) forming a first conducting layer on the first dielectric layer;
• d) removing the first conducting layer from the at least one memory cell area for forming a gate;
• e) forming source and drain regions in the body region for the at least one memory cell area;
• f) removing the first conducting layer and the first dielectric layer from the at least one high voltage transistor area;
• g) forming a second dielectric layer on the substrate for the at least one high voltage transistor area, on the gate and the first dielectric layer for the at least one memory cell area, and on the first conducting layer for the at least one low voltage transistor area;
• h) removing the second dielectric layer, the first conducting layer and the first dielectric layer from the at least one low voltage transistor area;
• i) forming a third dielectric layer on the substrate for the at least one low voltage transistor area;
• j) forming a second conducting layer on the third dielectric layer, and on the second dielectric layer for the at least one memory cell area and the at least one high voltage transistor area;
• and
• k) selectively removing the second conducting layer to form a gate for the at least one low voltage transistor, to form a gate for the at least one high voltage transistor, and to form a control gate for the at least one memory cell.

A process for forming an integrated circuit comprising at least one low voltage transistor, at least one high voltage transistor, and at least one memory cell, the process comprising:

• a) forming a body region in at least one low voltage transistor area in a substrate, a body region in at least one high voltage transistor area in the substrate, and a body region in at least one memory cell area in the substrate;
• b) forming a first dielectric layer on the substrate;
• c) forming a first conducting layer on the first dielectric layer;
• d) selectively removing the first conducting layer over the at least one memory cell area for forming a gate;
• e) forming source and drain regions in the body region for the at least one memory cell area by implanting dopant impurities through a mask into the at least one memory cell area while also using the first conducting layer over the low voltage and high voltage transistor areas as a mask;
• f) removing the first conducting layer and the first dielectric layer from the at least one high voltage transistor area;
• g) forming a second dielectric layer on the substrate for the at least one high voltage transistor area, on the gate and the first dielectric layer for the at least one memory cell area, and on the first conducting layer for the at least one low voltage transistor area;
• h) removing the second dielectric layer, the first conducting layer and the first dielectric layer from the at least one low voltage transistor area;
• i) annealing the substrate;
• j) forming a third dielectric layer on the substrate for the at least one low voltage transistor area;
• and
• k) forming a second conducting layer on the third dielectric layer, and on the second dielectric layer for the at least one memory cell area and the at least one high voltage transistor area.