US 6,319,772 B1 · Method for making low-leakage DRAM structures using selective silicon epitaxial growth (SEG) on an insulating layer

Abstract

Low current leakage DRAM structures are achieved using a selective silicon epitaxial growth over an insulating layer on memory cell (device) areas. An insulating layer, that also serves as a stress-release layer, and a Si3N4 hard mask are patterned to leave portions over the memory cell areas. Shallow trenches are etched in the substrate and filled with a CVD oxide which is polished back to the hard mask to form shallow trench isolation (STI) around the memory cell areas. The hard mask is selectively removed to form recesses in the STI aligned over the memory cell areas exposing the underlying insulating layer. Openings are etched in the insulating layer to provide a silicon-seed surface from which is grown a selective epitaxial layer extending over the insulating layer within the recesses. After growing a gate oxide on the epitaxial layer, FETs and DRAM capacitors can be formed on the epitaxial layer. The insulating layer under the epitaxial layer drastically reduces the capacitor leakage current and improves DRAM device performance. This self-aligning method also increases memory cell density, and is integratable into current DRAM processes to reduce cost.

Claims35

Dependent claims

A method for fabricating dynamic random access memory (DRAM) cells on and in an epitaxial silicon layer formed over a first insulating layer on a semiconductor substrate comprising the steps of:

forming said first insulating layer on said substrate;
depositing a hard-mask layer on said first insulating layer;
patterning said hard-mask layer and leaving portions over device areas, and using said hard mask for etching shallow trenches in said substate;
depositing a second insulating layer to fill said shallow trenches and polishing hack to said hard-mask layer to form shallow trench isolation;
selectively removing said hard-mask layer and forming recesses over and self-aligned to said device areas and exposing said first insulating layer in said recesses;
etching openings in said first insulating layer over device areas to said substrate;
growing selectively said epitaxial layer from said openings and extending laterally over said first insulating layer in said recesses;
forming a gate oxide on said epitaxial layer;
forming a doped polysilicon layer on said substrate;
patterning said polysilicon layer to form FET gate electrodes over said openings, and implanting to form lightly doped source/drain areas in said epitaxial layer adjacent to said gate electrodes;
forming insulating sidewall spacers on said gate electrodes, and implanting to form first and second source/drain contact areas adjacent to said sidewall spacers;
forming capacitors electrically contacting said first source/drain contact areas and bit lines electrically contacting said second source/drain contact-areas to complete said DRAM cells.

9 more elements

A method for fabricating dynamic random access memory (DRAM) cells on and in an epitaxial silicon layer formed over a first insulating layer on a semiconductor substrate comprising the steps of:

forming said first insulating layer on said substrate;
depositing a hard-mask layer on said first insulating layer;
patterning said hard-mask layer and leaving portions over device areas, and using said hard mask for etching shallow trenches in said substrate;
depositing a second insulating layer to fill said shallow trenches and polishing back to said hard-mask layer to form shallow trench isolation;
selectively removing said hard-mask layer and forming recesses over and self-aligned to said device areas and exposing said first insulating layer in said recesses;
etching openings in said first insulating layer over said device areas to said substrate;
growing selectively said epitaxial layer from said openings and extending laterally over said first insulating layer in said recesses;
forming capacitor bottom electrodes in a portion of said epitaxial layer by doping;
forming a gate oxide on said epitaxial layer;
forming a doped polysilicon layer on said substrate;
patterning said polysilicon layer to form FET gate electrodes over said openings and to form capacitor top electrodes for said capacitors over said capacitor bottom electrodes and patterning said polysilicon layer to form resistors over said shallow trench isolation;
implanting to form lightly doped source/drain areas in said epitaxial layer adjacent to said gate electrodes;
forming insulating sidewall spacers on said gate electrodes, and implanting to form first and second source/drain contact areas adjacent to said sidewall spacers, wherein said first source/drain contact areas are contiguous with said capacitor bottom electrodes;
forming bit lines electrically contacting said second source/drain contact areas to complete said DRAM cells.

11 more elements

A method for fabricating dynamic random access memory (DRAM) cells on and in an epitaxial silicon layer formed over a first insulating layer on a semiconductor substrate comprising the steps of:

forming said first insulating layer on said substrate;
depositing a hard-mask layer on said first insulating layer;
patterning said hard-mask layer and leaving portions over device areas, and using said hard mask for etching shallow trenches in said substrate;
depositing a second insulating layer to fill said shallow trenches and polishing back to said hard-mask layer to form shallow trench isolation;
selectively removing said hard-mask layer and forming recesses over and self-aligned to said device areas and exposing said first insulating layer in said recesses;
etching openings in said first insulating layer over said device areas to said substrate;
growing selectively said epitaxial layer from said openings and extending laterally over said first insulating layer in said recesses;
forming a gate oxide on said epitaxial layer;
forming a doped polysilicon layer on said substrate;
patterning said polysilicon layer to form FET gate electrodes over said openings, and implanting to form lightly doped source/drain areas in said epitaxial layer adjacent to said gate electrodes;
forming insulating sidewall spacers on said gate electrodes, and implanting to form first and second source/drain contact areas adjacent to said sidewall spacers;
depositing a first interpolysilicon oxide (IPO1) layer and etching first contact openings to said first source/drain contact areas and forming stacked capacitors having node contacts in said first contact openings;
depositing a second interpolysilicon oxide (IPO2) layer and etching second contact openings to said second source/drain contact areas and forming bit line contact plugs in said second contact openings and forming bit lines to complete said DRAM cells.

10 more elements

Dependencies are inferred from the claim text.

Method for making low-leakage DRAM structures using selective silicon epitaxial growth (SEG) on an insulating layer

Life of this patent

Method for making low-leakage DRAM structures using selective silicon epitaxial growth (SEG) on an insulating layer

Life of this patent

Abstract

Claims35