Method for fabricating a memory device with a high dielectric capacitor

A method for fabricating a memory device with a high dielectric capacitor comprising the steps of:

• forming an intermetal insulating layer provided with a contact hole exposing a junction region formed on a semiconductor layer having the junction region;
• forming a contact plug within the contact hole;
• forming a barrier layer and a metal layer for lower electrode on the intermetal insulating layer successively;
• forming a lower electrode by patterning selected portions of the metal layer for lower electrode and the barrier layer;
• forming a high dielectric layer on a substrate on which the lower electrode is formed;
• and
• forming an upper electrode on the high dielectric layer,
• wherein the step of forming the upper electrode includes the steps of forming a first Pt layer on the high dielectric layer according to a metal-organic chemical vapor deposition (MOCVD) method by providing an F-containing vapor or gas;
• and forming a second Pt layer on the first Pt layer, and wherein during the formation of the upper electrode, F atoms are included at an interface between the upper electrode and the high dielectric layer.