Mold compound selection for TSOP post mold cure processing
AssigneeAdvanced Micro Devices, Inc.
InventorJeffrey James Pollock
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Abstract
Warpage-free post-mold curing (PMC) of encapsulated device arrays, e.g., TSOPs, is performed without requiring placement of heavy metal weights on the arrays by utilization of molding/encapsulant materials having reduced coefficients of thermal expansion (CTE) and increased flexural moduli at both high and low temperature. Good lead co-planarity is maintained subsequent to PMC as a result of better matching of the encapsulant/molding material properties with those of the IC chip, lead frame, and substrate (e.g., Cu or Cu-based).
Claims17
A method of making at least one packaged electrical device or component, comprising the steps of:
- (a) providing an elongated, strip-shaped substrate having a major surface adapted for mounting thereon an array comprising a plurality of spaced-apart electrical devices or components;
- (b) providing and mounting said plurality of electrical devices or components in a spaced-apart array on said major surface of said substrate;
- (c) encapsulating said array of electrical devices or components by molding utilizing a molding material selected to provide substantially no, or at least minimal, warping of said array or said substrate upon completion of a post-mold curing treatment performed without placement of a heavy weight on said array, wherein step (c) comprises encapsulating utilizing a molding material having a filler content on the order of from about 80 to about 90 wt. %. reduced coefficients of thermal expansion (CTE) α1 and α2 on the order of about 1×10−5/° C. and about 4×10−5/° C. respectively, and increased low and high temperature flexural moduli on the order of about 2,500 kgf/mm2 and about 100 kgf/mm2, respectively;
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- (d) performing said post-mold curing of the encapsulated array at an elevated temperature and for a time sufficient to complete curing of said molding material with substantially no, or at least minimal, warping of said array or said substrate leading to loss of electrical lead co-planarity.
A method of making at least one TSOP structure, comprising the steps of:
- (a) providing an elongated, strip-shaped substrate having a major surface for mounting thereon a spaced-apart array comprising a plurality of low profile semiconductor integrated circuit (IC) devices in the form of dies or chips, each IC die or chip including a plurality of co-planar electrical leads extending therefrom for connection to circuitry on said substrate major surface;
- (b) mounting said plurality of IC dies or chips in spaced-apart array on said substrate major surface;
- (c) encapsulating said array of IC dies or chips by molding utilizing a molding material selected to provide substantially no, or at least minimal, warping of said array of IC dies or chips or said substrate upon completion of post-mold curing treatment without placement of a heavy weight on said array, thereby maintaining substantial co-planarity of said electrical leads, wherein step (c) comprises encapsulating utilizing an epoxy resin-based molding material having a filler content on the order of from about 80 to about 90 wt. %, reduced coefficients of thermal expansion (CTE) α1 and α2 on the order of about 1×10−5/° C. and about 4×1031 5/° C., respectively and increased low and high temperature flexural moduli on the order of about 2,500 kgf/mm2 and about 100 kgf/mm2, respectively;
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- (d) performing said post-mold curing of the encapsulated array at an elevated temperature and for a time sufficient to complete curing of said molding material with substantially no, or at least minimal, warping of said array or said substrate.
Dependencies are inferred from the claim text.