Zig-zagged plating bus lines
AssigneeSt Assembly Test Services Pte Ltd
InventorsArvin Verdeflor, Albert Loh, Steven Liew, William S. Villaviray
Life of this patent
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Abstract
A new pattern is provided for the bus lines that are used to facilitate plating of layers of electrical lines that form a Printed Circuit Board. Where Prior Art bus lines have a straight-line geometry, the bus lines of the invention have any geometry that is not a straight-line geometry. The geometry of the bus lines of the invention can be of any design as long as this design allows for interrupted cutting of the bus line, that is the cutting tool does not, during the process of cutting the bus line, make constant and continuous contact with the bus line.
Claims9
A method for creating interconnect wires in successive layers of Printed Circuit Boards, comprising the steps of:
- providing a first layer of a partially completed PCB circuit board;
- depositing a first layer of metal over the surface of said first layer of said partially completed PCB;
- patterning and etching said first layer of metal thereby forming a first interconnect pattern of said PCB;
- plating said first interconnect pattern thereby creating the first interconnect layer of metal of said PCB whereby hereafter said first interconnect layer is referred to as the preceding interconnect layer;
- providing a following layer of a partially completed PCB circuit board whereby said following layer of partially completed PCB board follows said preceding interconnect layer in the sequence of the creation of said PCB;
- depositing a following layer of metal over the surface of said following layer of said partially completed PCB;
- patterning and etching said following layer of metal thereby forming a following interconnect pattern on the surface of said following layer of said PCB;
- plating said following interconnect pattern on the surface of said following interconnect layer thereby creating a following interconnect layer of metal on the surface of said following layer of said PCB;
- repeating the process of creating additional layers of said partially completed PCB by repeating the above processing steps starting with said step of providing a following layer of a partially completed PCB circuit board and ending with said step of plating said interconnect pattern on the surface of said following layer said repetition to occur a number of times that equals the required layers to be contained within said PCB minus one thereby completing the creation of said PCB;
- and
- separating said completed PCB into individual PCB units.
Dependencies are inferred from the claim text.