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US 6,313,681 B1Granted
Variable delay circuit
AssigneeNEC Corporation
InventorKiyoshi Yoshikawa
Life of this patent
Estimating the term…
Abstract
A variable delay circuit has a positive logic variable delay circuit which delays an edge of a signal which is input through an input terminal and a negative logic variable delay circuit which delays an edge of the signal input through an input terminal. Only an edge delayed in accordance with the set time is extracted from all the edges of a signal supplied from the positive logic variable delay circuit and all the edges of a signal supplied from the negative logic variable delay circuit in an extracting circuit of the variable delay circuit.
Claims13
A variable delay circuit comprising:
- an input terminal;
- a positive logic variable delay circuit for delaying a leading edge of the signal inputted through said input terminal;
- a negative logic variable delay circuit for delaying a trailing edge of the signal inputted through said input terminal;
- and
- an extracting circuit for extracting only the edges delayed in accordance with a set time from the edges of a signal supplied from said positive logic variable delay circuit and the edges of a signal supplied from said negative logic variable delay circuit
- wherein said positive logic variable delay circuit includes
- delay time increasing means for making more than the set time, the delay time of an edge, varying from a low level to a high level, of the signal inputted through said input terminal, while
- said negative logic variable delay circuit includes
- delay time decreasing means for making less than the set time, the delay time of an edge, varying from a high level to a low level, of the signal inputted through said input terminal.
6 more elements
A variable delay circuit comprising:
- an input terminal;
- a positive logic variable delay circuit for delaying a leading edge of the signal inputted through said input terminal;
- a negative logic variable delay circuit for delaying a trailing edge of the signal inputted through said input terminal;
- and
- an extracting circuit for extracting only the edges delayed in accordance with a set time from the edges of a signal supplied from said positive logic variable delay circuit and the edges of a signal supplied from said negative logic variable delay circuit
- wherein said positive logic variable delay circuit includes
- delay time increasing means for making more than the set time, the delay time of an edge, varying from a low level to a high level, of the signal inputted through said input terminal, while
- said negative logic variable delay circuit includes
- delay time decreasing means for making less than the set time, the delay time of an edge, varying from a high level to a low level, of the signal inputted through said input terminal, and
- said extracting circuit is an OR circuit which computes OR of the signal supplied from said positive logic variable delay circuit and the signal supplied from said negative logic variable delay circuit.
7 more elements
A variable delay circuit comprising:
- an input terminal;
- a positive logic variable delay circuit for delaying a leading edge of the signal inputted through said input terminal;
- a negative logic variable delay circuit for delaying a trailing edge of the signal inputted through said input terminal;
- and
- an extracting circuit for extracting only the edges delayed in accordance with a set time from the edges of a signal supplied from said positive logic variable delay circuit and the edges of a signal supplied from said negative logic variable delay circuit
- wherein said positive logic variable delay circuit includes
- delay time increasing means for making more than the set time, the delay time of an edge, varying from a low level to a high level, of the signal inputted through said input terminal, while
- said negative logic variable delay circuit includes
- delay time decreasing means for making less than the set time, the delay time of an edge, varying from a high level to a low level, of the signal inputted through said input terminal,
- said delay time increasing means and said delay time decreasing means respectively including a capacitive element and adjusting the delay time by setting the capacity of the capacitive element.
7 more elements
A variable delay circuit comprising:
- an input terminal;
- a positive logic variable delay circuit for delaying a leading edge of the signal inputted through said input terminal;
- a negative logic variable delay circuit for delaying a trailing edge of the signal inputted through said input terminal;
- and
- an extracting circuit for extracting only the edges delayed in accordance with a set time from the edges of a signal supplied from said positive logic variable delay circuit and the edges of a signal supplied from said negative logic variable delay circuit
- wherein said positive logic variable delay circuit includes
- a first delay circuit for delaying an edge, varying from a high level and a low level, of the signal inputted through said input terminal and supplying the logic being inverted, and
- a second delay circuit for delaying an edge, varying from a high level to a low level, of a signal supplied from said first delay circuit and supplying the logic being inverted, while
- said negative logic variable delay circuit includes
- a first inverter for inverting the logic of the signal inputted through said input terminal,
- a third delay circuit for delaying an edge, varying from a high level to a low level, of a signal supplied from said first inverter and supplying the logic being inverted,
- a fourth delay circuit for delaying an edge, varying from a high level to a low level, of a signal supplied from said third delay circuit and supplying the logic being inverted, and
- a second inverter for inverting the logic of a signal supplied from said fourth delay circuit.
10 more elements
A variable delay circuit comprising:
- an input terminal;
- a positive logic variable delay circuit for delaying a leading edge of the signal inputted through said input terminal;
- a negative logic variable delay circuit for delaying a trailing edge of the signal inputted through said input terminal;
- and
- an extracting circuit for extracting only the edges delayed in accordance with a set time from the edges of a signal supplied from said positive logic variable delay circuit and the edges of a signal supplied from said negative logic variable delay circuit
- wherein said positive logic variable delay circuit includes
- delay time increasing means for making more than the set time, the delay time of an edge, varying from a low level to a high level, of the signal inputted through said input terminal,
- a first delay circuit for delaying an edge, varying from a low level to a high level, of the signal inputted through said input terminal and supplying the logic being inverted, and
- a second delay circuit for delaying an edge, varying from a high level to a low level, of a signal supplied from said first delay circuit and supplying the logic being inverted, while
- said negative logic variable delay circuit includes delay time decreasing means for making less than the set time, the delay time of an edge, varying from a high level to a low level, of the signal inputted through said input terminal,
- a first inverter for inverting the logic of a signal input through said input terminal,
- a third delay circuit for delaying an edge, varying from a high level to a low level, of a signal supplied from said first inverter and supplying the logic being inverted,
- a fourth delay circuit for delaying an edge, varying from a high level to a low level, of a signal supplied from said third delay circuit and supplying the logic being inverted, and
- a second inverter for inverting the logic of a signal supplied from said fourth delay circuit.
11 more elements
A variable delay circuit comprising:
- an input terminal;
- a positive logic variable delay circuit for delaying a leading edge of the signal inputted through said input terminal;
- a negative logic variable delay circuit for delaying a trailing edge of the signal inputted through said input terminal;
- and
- an extracting circuit for extracting only the edges delayed in accordance with a set time from the edges of a signal supplied from said positive logic variable delay circuit and the edges of a signal supplied from said negative logic variable delay circuit
- wherein said positive logic variable delay circuit includes
- a first delay circuit for delaying an edge, varying from a high level to a low level, of the signal inputted through said input terminal and supplying the logic being inverted, and
- a second delay circuit for delaying an edge, varying from a high level to a low level, of a signal supplied from said first delay circuit and supplying the logic being inverted, while
- said negative logic variable delay circuit includes
- a first inverter for inverting the logic of the signal inputted through said input terminal,
- a third delay circuit for delaying an edge, varying from a high level to a low level, of a signal supplied from said first inverter and supplying the logic being inverted,
- a fourth delay circuit for delaying an edge, varying from a high level to a low level, of a signal supplied from said first inverter and supplying the logic being inverted,
- a second inverter for inverting the logic of a signal supplied from said fourth delay circuit,
- said first delay circuit including
- a first capacitive element which is charged upon receipt of an edge varying from a low level to a high level and discharged upon receipt of an edge varying from a high level to a low level,
- said second delay circuit including
- a second capacitive element which is charged upon receipt of an edge varying from a low level to a high level and discharged upon receipt of an edge varying from a high to a low level,
- said third delay circuit including
- a third capacitive element which is charged upon receipt of an edge varying from a low level to a high level and discharged upon receipt of an edge varying from a high to a low level,
- said fourth delay circuit including
- a fourth capacitive element which is charged upon receipt of an edge varying from a low level to a high level and discharged upon receipt of an edge varying from a high level to a low level.
18 more elements
A variable delay circuit comprising:
- an input terminal;
- a positive logic variable delay circuit for delaying a leading edge of the signal inputted through said input terminal;
- a negative logic variable delay circuit for delaying a trailing edge of the signal inputted through said input terminal;
- and
- an extracting circuit for extracting only the edges delayed in accordance with a set time from the edges of a signal supplied from said positive logic variable delay circuit and the edges of a signal supplied from said negative logic variable delay circuit
- wherein said positive logic variable delay circuit includes
- a first delay circuit for delaying an edge, varying from a high level to a low level, of the signal inputted through said input terminal and supplying the logic being inverted, and
- a second delay circuit for delaying an edge, varying from a high level to a low level, of a signal supplied from said first delay circuit and supplying the logic being inverted, while
- said negative logic variable delay circuit includes
- a first inverter for inverting the logic of the signal inputted through said input terminal,
- a third delay circuit for delaying an edge, varying from a high level to a low level, of a signal supplied for said first inverter and supplying the logic being inverted,
- a fourth delay circuit for delaying an edge, varying from a high level to a low level, of a signal supplied from said third delay circuit and supplying the logic being inverted, and
- a second inverter for inverting the logic of a signal supplied from said fourth delay circuit,
- said first delay circuit including
- a first capacitive element which is charged upon receipt of an edge varying from a low level to a high level and
- a first constant-current power for discharging said first capacitive element upon receipt of a edge varying from a high level to a low level,
- said second delay circuit including
- a second capacitive element which is charged upon receipt of an edge varying from a low level to a high level and
- a second constant-current power for discharging said second capacitive element upon receipt of an edge varying from a high to a low level,
- said third delay circuit including
- a third capacitive element which is charged upon receipt of an edge varying from a low level to a high level and
- a third constant-current power for discharging said third capacitive element upon receipt of an edge varying from a high level to a low level,
- said fourth delay circuit including
- a fourth capacitive element which is charged upon receipt of an edge varying from a low level to a high level and
- a fourth constant-current power for discharging said fourth capacitive element upon receipt of an edge varying from a high level to a low level.
22 more elements
A variable delay circuit comprising:
- an input terminal;
- a positive logic variable delay circuit for delaying a leading edge of the signal inputted through said input terminal;
- a negative logic variable delay circuit for delaying a trailing edge of the signal inputted through said input terminal;
- and
- an extracting circuit for extracting only the edges delayed in accordance with a set time from the edges of a signal supplied from said positive logic variable delay circuit and the edges of a signal supplied from said negative logic variable delay circuit
- wherein said extracting circuit includes
- a first fixed delay circuit for generating a constant delay on the signal supplied from said positive logic variable delay circuit,
- an OR circuit for calculating OR of a signal supplied from said first fixed delay circuit and the signal supplied from said negative logic variable delay circuit,
- a second fixed delay circuit for generating the constant delay on a signal supplied from said OR circuit, and
- an AND circuit for calculating AND of a signal supplied from said second fixed delay circuit and a signal supplied from said OR circuit.
7 more elements
A variable delay circuit comprising:
- an input terminal;
- a positive logic variable delay circuit for delaying a leading edge of the signal inputted through said input terminal;
- a negative logic variable delay circuit for delaying a trailing edge of the signal inputted through said input terminal;
- and
- an extracting circuit for extracting only the edges delayed in accordance with a set time from the edges of a signal supplied from said positive logic variable delay circuit and the edges of a signal supplied from said negative logic variable delay circuit
- wherein said positive logic variable delay circuit includes
- delay time increasing means for making more than the set time, the delay time of the edge, varying from a low level to a high level, of the signal inputted through said input terminal, while
- said negative logic variable delay circuit includes
- delay time decreasing means for making less than the set time, the delay time of the edge, varying from a high level to a low level, of the signal inputted through said input terminal, and
- said extracting circuit includes
- a first fixed delay circuit for generating a constant delay on a signal supplied from said positive logic variable delay circuit,
- an OR circuit for calculating OR of a signal supplied from said first fixed delay circuit and a signal supplied from said negative logic variable delay circuit,
- a second fixed delay circuit for generating the constant delay on a signal supplied from said OR circuit, and
- an AND circuit for calculating AND of a signal supplied from said second fixed delay circuit and a signal supplied from said OR circuit.
11 more elements
Dependencies are inferred from the claim text.