Semiconductor die having input/output cells and contact pads in the periphery of a substrate
AssigneeOki Electric Industry Co., Ltd.
InventorShinichiro Watanabe
Life of this patent
Estimating the term…
Abstract
The width of an input/output forming region is matched with the minimum width adoptable as a layout interval between pads in advance. Pads corresponding to (least common multiple)÷(layout interval between pads) in number are disposed so as to correspond to input/output cells corresponding to (least common multiple)÷(width of input/output cell forming region) in number, based on the least common multiple between the width of each input/output cell forming region and the layout interval between the pads. Owing to such a construction, a semiconductor device can be provided which meets user demands with ease and in a short time.
Claims20
A semiconductor device including a semiconductor chip having a central area, a peripheral area that surrounds said central area and four sides that bound said peripheral area, said semiconductor chip comprising:
- a main circuit region formed in the central area of said semiconductor chip;
- a plurality of input/output cells in said peripheral area of said semiconductor chip, wherein said input/output cells a re arranged in rows that are each parallel to a respective one of said four sides of said semiconductor chip, and each of said input/output cells has a width of a length n that extends in the direction in which the respective row extends;
- a plurality of pads in an exterior portion of said peripheral area of said semiconductor chip beyond said input/output cells, wherein said pads are arranged in rows that are parallel to respective rows of said input/output cells, and wherein a layout interval between the center of adjacent pads in each of said rows is a distance m;
- and
- a plurality of interconnections, each of which electrically connects one of said plurality of pads to one of said plurality of input/output cells.
A semiconductor application specific integrated circuit (ASIC) device including a semiconductor chip having a central area and a peripheral area that surrounds said central area, said semiconductor chip comprising:
- a main circuit forming region formed in said central area of said semiconductor chip;
- a plurality of input/output cells arranged in a line within said peripheral area of said semiconductor chip, and each of said input/output cells has a width n;
- a plurality of pads formed in said peripheral area of said semiconductor chip beyond said input/output cells, wherein a layout interval between the center of adjacent pads is a distance m;
- and
- a plurality of interconnections, each of which electrically connects one of said plurality of pads to one of said input/output cells.
A semiconductor device including a semiconductor chip having a peripheral area that surrounds said central area, said semiconductor chip comprising:
- a main circuit forming region formed in said central area;
- a plurality of input/output cells arranged in a line within said peripheral area, each of said cells having a same width and including a semiconductor element;
- a plurality of pads formed in said peripheral area beyond said cells, wherein a layout interval between the centers of each adjacent pair of the pads is a same distance;
- and
- a plurality if conductors, each electrically connecting one of said plurality of pads to one of said cells.
Dependencies are inferred from the claim text.