Butted contact resistance of an SRAM by double VCC implantation

A butted contact in an SRAM memory device comprising:

• an SRAM memory device with a butted contact including:
• a) a contact region on the surface of a doped semiconductor substrate,
• b) a conductor stack above a field oxide region on the surface of said substrate;
• an interpolysilicon silicon oxide dielectric layer on the surface of said device with an opening framing said contact region and a butt end of said conductor stack adjacent to said contact region,
• a doped upper polysilicon layer on the surface of said SRAM device covering said interpolysilicon silicon oxide dielectric layer, said contact region, and the butt end of said conductor stack,
• a first dose of Vcc dopant implanted into said upper polysillcon layer at a first energy level,
• ion implanting a second dose of Vcc dopant through a window into said contact region and said butt end of said conductor stack layer at a higher energy level than said first energy level,
• said upper polysilicon layer was implanted with said first dose of Vcc dopant comprising phosphorus dopant from about 2 E 15 ionslcm2 to about 6 E 15 ions/cm2 at an energy from about 30 keV to about 40 keV, and after annealing the concentration of phosphorus dopant in the upper polysilicon layer is from about 2 E 20 atoms/cm3 to about 6 E 20 atoms/cm3, and
• said buried contact region and said butt end of said conductor stack were implanted with said second dose of Vcc dopant comprising phosphorus dopant from about 2 E 15 ions/cm2 to about 6 E 15 ions/cm2 at an energy from about 45 keV to about 65 keV.

A butted contact in an SRAM memory device comprising:

• an SRAM memory device with a butted contact including:
• a) a contact region on the surface of a doped semiconductor substrate,
• b) a conductor stack above a field oxide region on the surface of said substrate;
• an interpolysilicon silicon oxide dielectric layer on the surface of said device with an opening framing said contact region and a butt end of said conductor stack adjacent to said contact region,
• a doped upper polysilicon layer on the surface of said SRAM device covering said interpolysilicon silicon oxide dielectric layer, said contact region, and the butt end of said conductor stack,
• a first dose of Vcc dopant implanted into said upper polysilicon layer at a first energy level,
• ion implanting a second dose of Vcc dopant through a window into said contact region and said butt end of said conductor stack layer at a higher energy level than said first energy level,
• said upper polysilucon layer was implanted with said first dose of about 4 E 15 ions/cm2 Vcc dopant comprising phosphorus at an energy of 35 keV and after annealing the concentration of phosphorus dopant in the upper polysilicon layer is from about 2 E 20 atoms/cm3 to about 6 E 20 atoms/em3, and
• said buried contact region and said butt end of said conductor stack were implanted with said second dose of about 4 E 15 ions/cm2 Vcc dopant comprising phosphorus dopant at an energy of 50 keV.