NMOS triggered NMOS ESD protection circuit using low voltage NMOS transistors

A digital system comprising:

• a first integrated circuit having an output buffer operable to provide an output signal on a first terminal having fist signal voltage level;
• a second integrated circuit having an output buffer with a signal bond pad connected to the first terminal, wherein the second integrated circuit further comprises:
• a semiconductor substrate connected to a reference bond pad for a reference supply voltage;
• a first bus for a first supply voltage, wherein the first signal voltage level is higher than the first supply voltage;
• internal circuitry connected between the first bus and semiconductor substrate comprising MOS transistors having gate oxide with a first thickness having a Vox-max suitable for the first supply voltage but not for the first signal voltage;
• ESD circuitry connected between the signal pad and the reference bond pad, wherein the ESD circuitry comprises:
• a first substrate region in the semiconductor substrate enclosed by a highly doped region;
• a first string of cascode connected MOS transistors each having gate oxide of the first thickness, each with a backgate in the first substrate region, a first source/drain connected to the signal pond pad, a last source/drain connected to the reference bond pad, and a separate control gate associated with each of the MOS transistors in the first string;
• a second string of cascode connected MOS transistors each having a gate oxide of the first thickness, with a first source/drain connected to the signal bond pad, a last source/drain connected to the highly doped region, and a separate control gate associated with each of the MOS transistors in the second string;
• and
• control circuitry connected to the first signal bond pad and to each of the gates in the first string and the second string operable to provide a voltage pulse to each gate in the first string and to each gate in the second string in response to an ESD zap applied to the first signal bond pad.

A method for providing electrostatic protection for an integrated circuit, wherein the integrated circuit has internal circuitry operable at a first supply voltage and a first signal bond pad for connecting to an external signal, wherein the external signal is operable at approximately a second supply voltage and the second supply voltage is higher than the first supply voltage, and wherein the internal circuitry has MOS transistors with gate oxide having a first thickness with a Vox-max suitable for the first supply voltage but not for the second supply voltage, comprising the steps of:

• enclosing a first substrate region in a semiconductor substrate of the integrated circuit by a highly doped region;
• connecting a first string of cascode connected MOS transistors having gate oxide of the first thickness between the signal bond pad and a reference bond pad, such that a backgate of each is in the first substrate region;
• connecting a second string of cascode connected MOS transistors having a gate oxide of the first thickness between the signal bond pad and the highly doped region,
• coupling control gates of the first string of cascode connected MOS transistors and control gates of the second string of cascode connected MOS transistors to the signal bond pad;
• pumping the first substrate region in response to an ESD zap applied to the first signal bond pad by turning on the second string of cascode connected MOS transistors via the coupled control gates;
• and
• turning on the first string of cascode connected MOS transistors in response to the ESD zap via the coupled control gates before the second string of cascode connected transistors and the internal circuitry is damaged by the ESD zap.