Nonvolatile semiconductor memory device having extracting electrode
AssigneeKabushiki Kaisha Toshiba
InventorsShinji Satoh, Riichiro Shirota, Seiichi Aritome
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Abstract
This invention is a nonvolatile semiconductor memory device including an electrically rewritable memory cell having a gate, source, drain, and charge storage layer, an extracting electrode electrically connected to at least one of the source and drain of the memory cell, and a counter electrode essentially capacitively coupled with the extracting electrode.
Claims22
A nonvolatile semiconductor memory device comprising:
- an electrically rewritable memory cell having a gate, source, drain, and charge storage layer;
- and
- an extracting electrode directly connected to at least one of the source and drain of said memory cell and capacitively coupled with the gate.
A nonvolatile semiconductor memory device comprising:
- an electrically rewritable memory cell having a gate, source, drain, and charge storage layer;
- an extracting electrode directly connected to at least one of the source and drain of said memory cell and capacitively coupled with the gate;
- and
- a counter electrode substantially capacitively coupled with said extracting electrode.
A nonvolatile semiconductor memory device comprising:
- a cell unit in which a plurality of electrically rewritable memory cells each having a gate, source, drain, and charge storage layer are connected to make adjacent memory cells share one of their sources and one of their drains;
- an extracting electrode directly contacting at least one of the source and drain in said cell unit and capacitively coupled with the gate;
- and
- a counter electrode substantially capacitively coupled with said extracting electrode.
A nonvolatile semiconductor memory device comprising:
- a cell unit in which a plurality of electrically rewritable memory cells each having a gate, source, drain, and charge storage layer are connected to make adjacent memory cells share one of the sources and one of the drains;
- and
- an extracting electrode directly contacting at least one of the source and drain in said cell unit and capacitively coupled with the gate.
A nonvolatile semiconductor memory device comprising:
- a plurality of cell units which are integrated in a matrix manner to form a memory cell array, wherein each of the plurality of cell units has a plurality of electrically rewritable memory cells, each having a gate, source, drain, and charge storage layer, connected to make adjacent memory cells share one of the sources and one of the drains;
- and
- an extracting electrode directly contacting at least one of the source and drain in said cell unit capacitively coupled with the gate, wherein said extracting electrode is formed in each cell unit.
Dependencies are inferred from the claim text.