Film stack and etching sequence for dual damascene

A process for forming a dual damascene cavity, that comprises a via hole and a trench, in a first dielectric layer, comprising:

• forming said dielectric layer from first upper and lower layers separated by a first etch stop layer;
• forming, on said first upper dielectric layer, a hard mask layer that further comprises second upper and lower dielectric layers, separated by a second etch stop layer;
• patterning and etching the upper second dielectric layer to form an incomplete trench that extends as far as the second etch stop layer and then removing any exposed portions of the second etch stop layer;
• patterning and etching the hard mask to form an incomplete via hole that extends as far as the first upper dielectric layer wherein the via hole is defined inside the trench;
• and
• selectively etching all exposed surfaces whereby the via hole extends through the first lower dielectric layer and the trench extends as far as the first etch stop layer.

A process for forming a trench and via cavity, comprising:

• providing a partially completed integrated circuit;
• depositing, in sequence on said integrated circuit, a first dielectric layer, an etch stop layer, and a second dielectric layer;
• depositing a first layer of silicon oxynitride on said second dielectric layer;
• depositing a layer of silicon oxide on said first layer of silicon oxynitride;
• depositing a second layer of silicon oxynitride on the layer of silicon oxide;
• laying down a first photoresist mask that defines a via hole, then etching the second layer of silicon oxynitride down to the level of the silicon oxide, and then removing the photoresist;
• laying down a second photoresist mask that defines a trench which encompasses said via hole;
• then etching the first and second silicon oxynitride layers and the silicon oxide layer down to the level of the second dielectric layer;
• removing all photoresist and then, using the first and second silicon oxynitride layers as a hard mask, etching the second dielectric layer down to the etch stop layer;
• removing all exposed portions of the etch stop layer;
• and
• etching the first and second dielectric layers until the trench extends as far as the etch stop layer and the via hole extends down to the level of the integrated circuit.

A process for forming a trench and via cavity, comprising:

• providing a partially completed integrated circuit;
• depositing, in sequence on said integrated circuit, a first dielectric layer, an etch stop layer, and a second dielectric layer;
• depositing a first layer of silicon oxynitride on said second dielectric layer;
• depositing a layer of silicon oxide on said first layer of silicon oxynitride;
• depositing a second layer of silicon oxynitride on the layer of silicon oxide;
• laying down a first photoresist mask that defines a trench, then etching the second layer of silicon oxynitride down to the level of the silicon oxide, and then removing the photoresist;
• laying down a second photoresist mask that defines a via hole that is wholly within said trench;
• then etching the first silicon oxynitride layer and the silicon oxide layer down to the level of the second dielectric layer;
• removing all photoresist and then, using the first and second silicon oxynitride layers as a hard mask, etching the second dielectric layer down to the etch stop layer;
• removing all exposed portions of the etch stop layer;
• and
• etching the first and second dielectric layers until the trench extends as far as the etch stop layer and the via hole extends down to the level of the integrated circuit.