Latch-up resistant CMOS structure

A method of fabricating a semiconductor device comprising:

• forming a field oxide layer on a semiconductor substrate having a first conductivity type where the semiconductor substrate includes first and second MOS transistor regions and first and second contact regions;
• forming a first well having a second conductivity type in the semiconductor substrate that includes the first MOS transistor region and the first contact region;
• forming a first heavily doped region having the second conductivity type in the semiconductor substrate corresponding to the first contact region in the first well, wherein the first heavily doped region does not extend below the first MOS transistor in the first well;
• forming a second well having the first conductivity type in the semiconductor substrate that includes the second MOS transistor region and the second contact region;
• and
• forming a second heavily doped region having the first conductivity type in the semiconductor substrate corresponding to the second contact region in the second well.

A method of fabricating a semiconductor device, comprising:

• forming a field oxide layer on a semiconductor substrate that includes first and second MOS transistor regions and first and second contact regions;
• forming a first well having a second conductivity type in the semiconductor substrate, wherein the first well includes the first MOS transistor region and the first contact region;
• forming a first heavily doped region having the second conductivity type in the first well corresponding to the first contact region;
• forming a second well having the first conductivity type in the semiconductor substrate, wherein the second well includes the second MOS transistor region and the second contact region;
• forming a second heavily doped region having the first conductivity type in the second well corresponding to the second contact region, wherein the second heavily doped region does not extend below a second MOS transistor in the second well;
• connecting a first prescribed voltage to the first contact region and a first electrode of the first MOS transistor;
• and
• connecting a second prescribed voltage to the second contact region and a first electrode of the second MOS transistor.