Method of forming high K tantalum pentoxide Ta2O5 instead of ONO stacked films to increase coupling ratio and improve reliability for flash memory devices

A method of forming a high K interpoly dielectric layer between a floating gate and a control gate in a flash memory cell comprising a substrate, a tunnel oxide over the substrate, the floating gate over the tunnel oxide, the high K interpoly dielectric layer on the floating gate, and the control gate on the high K interpoly dielectric layer, wherein the high K interpoly dielectric layer consists essentially of an oxide layer over the floating gate, and a tantalum pentoxide layer over the oxide layer, comprising:

• forming an oxide layer having a thickness from about 30 Å to about 70 Å at a temperature below about 900° C.;
• and
• forming a tantalum pentoxide layer over the oxide layer, wherein the tantalum pentoxide layer is deposited by chemical vapor deposition using an organic tantalum compound, an oxygen compound and a carrier gas at a temperature below about 700° C., and heating in an N2O atmosphere at a temperature below about 900° C.,
• wherein the high K interpoly dielectric layer has a dielectric constant of at least about 20.

A method of forming a flash memory cell, comprising:

• forming a tunnel oxide on a substrate;
• forming a first polysilicon layer over the tunnel oxide;
• forming an insulating layer on the first polysilicon layer, the insulating layer consisting essentially of an oxide layer over the first polysilicon layer, and a tantalum pentoxide layer over the oxide layer, wherein the tantalum pentoxide layer is made by chemical vapor deposition at a temperature from about 200° C. to about 650° C. using an organic tantalum compound and an oxygen compound, and heating in an N2O atmosphere at a temperature from about 700° C. to about 875° C.;
• forming a second polysilicon layer on the insulating layer;
• forming a tungsten silicide layer over the second polysilicon layer;
• etching at least the first polysilicon layer, the second polysilicon layer, the insulating layer and the tungsten silicide layer, thereby defining at least one stacked gate structure;
• and
• forming a source region and a drain region in the substrate, thereby forming at least one memory cell.