US 6,309,921 B1Granted

Semiconductor device and method for fabricating semiconductor device

AssigneeFujitsu Limited

InventorsTaiji Ema, Kazuo Itabashi, Shinichiroh Ikemasu, Junichi Mitani, Itsuo Yanagita, Seiichi Suzuki

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Abstract

The semiconductor device comprises a semiconductor substrate 10 of a first conduction-type, first wells 20a, 20b of a second conduction-type formed in a first region on the primary surface of the semiconductor substrate 10, a second well 22a formed in a second region on the primary surface of the semiconductor substrate 10 other than the first region, a third well 22b of the first conduction-type formed in the first well, and high-concentration impurity-doped layers 26 of the first conduction-type formed in deep portions of the semiconductor substrate spaced from the primary surface of the semiconductor device in device regions. In the semiconductor device having triple wells according to the present invention, the high-concentration impurity-doped layers are formed in deep portions inside of the device regions. Accordingly, in the case where the wells have a low concentration so that the transistors have a low threshold voltage, the deep portions of the wells can independently have a high concentration. As a result, punch-through between the source/drain diffused layer of the transistor formed in the well in the well (double wells), and the well outside of the double wells can be prevented. This structure is also effective to prevent latch-up.

Claims14

Dependent claims

A method for fabricating a semiconductor device comprising the steps of:

forming on a semiconductor substrate of a first conductivity-type a first resist pattern with a first opening formed in a first region and with a second opening formed in a second region other than the first region;
doping a first impurity of a second conductivity-type in the semiconductor substrate with the first resist pattern as a mask to form a first well of the second conductivity-type in the first region and a second well of the second conductivity-type in the second region;
removing the first resist pattern;
forming on the semiconductor substrate a second resist pattern with a third opening formed in a third region other than the first region and the second region and with a fourth opening formed in a fourth region within the first region;
doping a second impurity of the first conductivity-type in the semiconductor substrate with the second resist pattern as a mask to form a third well of the first conductivity-type in the third region and a fourth well of the first conductivity-type in the fourth region which is electrically isolated from a rest region of the semiconductor substrate by the first well, the step of doping the second impurity at least including a first ion implanting step of implanting a first dose of ions at a first acceleration energy, and a second ion implanting step of implanting a second dose of ions larger than the first dose of ions at a second acceleration energy higher than the first acceleration energy so that a position of a peak impurity concentration of the third well and that of the fourth well being located in the semiconductor substrate spaced from the surface thereof, the fourth well preventing a punch-through between a source/drain region of the third transistor and the first well;
removing the second resist pattern;
forming a first transistor of the first conductivity-type in the second well, a second transistor of the second conductivity-type in the third well, and a third transistor of the second conductivity-type in the fourth well.

4 more elements

A method for fabricating a semiconductor device comprising the steps of:

forming on a semiconductor substrate of a first conductivity-type a first resist pattern with a first opening formed in a first region and with a second opening formed in a second region other than the first region;
doping a first impurity of a second conductivity-type in the semiconductor substrate with the first resist pattern as a mask to form a first well of the second conductivity-type in the first region and a second well of the second conductivity-type in the second region;
forming on the semiconductor substrate a second resist pattern with a third opening formed in a third region other than the first region and the second region and with a fourth opening formed in a fourth region within the first region;
doping a second impurity of the first conductivity-type in the semiconductor substrate with the second resist pattern as a mask to form a third well of the first conductivity-type in the third region and a fourth well of the first conductivity-type in fourth region which is electrically isolated from a rest region of the semiconductor substrate by the first well;
removing the second resist pattern;
forming a third resist pattern with a fifth opening formed in the same region as the fourth region;
and
doping a third impurity of the first conductivity-type in the fourth region with a third resist pattern as a mask to form a high-concentration impurity-doped layer of the first conductivity-type buried in the fourth well, the high-concentration impurity-doped layer preventing a punch-through between a source/drain region of the third transistor and the first well;
removing the third resist pattern;
forming a first transistor of the first conductivity-type in the second well, a second transistor of the second conductivity-type in the third well, and a third transistor of the second conductivity-type in the fourth well;
and
before the step of forming the high-concentration impurity doped layer, forming a device isolation film which electronically isolates a plurality of semiconductor devices to be formed on the surface of the semiconductor substrate, the high-concentration impurity-doped layer being formed below the device isolation film in a region where the device isolation film is formed.

9 more elements

A method for fabricating a semiconductor device comprising the steps of:

forming on a semiconductor substrate of a first conductivity-type a first resist pattern with a first opening formed in a first region other than the first region;
doping a first impurity of a second conductivity-type in the semiconductor substrate with the first resist pattern as a mask to form a first well of the second conductivity-type in the first region and a second well of the second conductivity-type in the second region;
removing the first resist pattern;
forming on the semiconductor substrate a second resist pattern with a third opening formed in a third region other than the first region and the second region and with a fourth opening formed in a fourth region within the first region;
doping a second impurity of the first conductivity-type in the semiconductor substrate with the second resist pattern as a mask to form a third well of the first conductivity-type in the third region and a fourth well of the first conductivity-type in the fourth region which is electrically isolated from a rest region of the semiconductor substrate the first well, a position of a peak impurity concentration of the third well and that of the fourth well being located in the semiconductor substrate spaced from a surface thereof, the fourth well preventing a punch-through between a source/drain region of the third transistor and the first well;
removing the second resist pattern;
forming a first transistor of the first conductivity-type in the second well, a second transistor of the second conductivity-type in the third well, and a third transistor of the second conductivity-type in the third well, and a third transistor of the second conductivity-type in the fourth well;
and
before the step of forming the second resist pattern, forming a device isolation film which electronically isolates a plurality of semiconductor devices to be formed on the surface of the semiconductor substrate, the position of the peak impurity concentration of the third well and that of the fourth well being formed below the device isolation film in a region where the device isolation film is formed.

6 more elements

Dependencies are inferred from the claim text.