US 6,309,918 B1Granted

Manufacturable GaAs VFET process

AssigneeMotorola, Inc.

InventorsJenn-Hwa Huang, Benjamin W. Gable, Kurt Eisenbeiser, David Rhine

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Abstract

A manufacturable GaAs VFET process includes providing a doped GaAs substrate with a lightly doped first epitaxial layer thereon and a heavily doped second epitaxial layer positioned on the first epitaxial layer. A temperature tolerant conductive layer is positioned on the second epitaxial layer and patterned to define a plurality of elongated, spaced apart source areas. Using the patterned conductive layer, a plurality of gate trenches are etched into the first epitaxial layer adjacent the source areas. The bottoms of the gate trenches are implanted and activated to form gate areas. A gate contact is deposited in communication with the implanted gate areas, a source contact is deposited in communication with the patterned conductive layer overlying the source areas, and a drain contact is deposited on the rear surface of the substrate.

Claims18

Dependent claims

A manufacturable GaAs VFET process comprising the steps of:

providing a substrate structure including a doped GaAs supporting substrate, a lightly doped first epitaxial layer including GaAs positioned on a first surface of the supporting substrate, and a heavily doped second epitaxial layer including GaAs positioned on the first epitaxial layer;
depositing a temperature tolerant conductive layer on the second epitaxial layer;
patterning the conductive layer to define a plurality of source areas underlying portions of patterned conductive layer;
using the portions of patterned conductive layer, etching a plurality of gate trenches into the first epitaxial layer of the substrate structure adjacent the source areas, the gate trenches having bottoms spaced vertically from the second epitaxial layer;
implanting material in the bottoms of the gate trenches to form implanted gate areas in the gate trenches and activating the implanted gate areas;
depositing a gate contact in communication with the implanted gate areas by depositing a thin metal layer on the implanted gate areas to reduce gate resistance wherein the step of etching the plurality of gate trenches included undercutting the portions of patterned conductive layer to prevent metal from being deposited on trench sides during the step of depositing the thin metal layer on the implanted gate areas;
depositing a source contact in communication with the portions of patterned conductive layer overlying the source areas;
and
depositing a drain contact on a second surface of the substrate structure.

6 more elements

A manufacturable GaAs VFET process comprising the steps of:

providing a substrate structure including a doped GaAs supporting substrate, a lightly doped first epitaxial layer including GaAs positioned on a first surface of the supporting substrate, and a heavily doped second epitaxial layer including GaAs positioned on the first epitaxial layer;
depositing a temperature tolerant conductive layer on the second epitaxial layer where the temperature tolerance is such that the layer of conductive material remains a layer during annealing for activation of implanted areas;
pattering the conductive layer to define a plurality of spaced apart, elongated source areas underlying portions of patterned conductive layer;
using the portions of patterned conductive layer, etching a plurality of gate trenches into the first epitaxial layer of the substrate structure adjacent the source areas so as to form elongated raised fingers between the gate trenches with the elongated source areas underlying portions of patterned conductive layer on an upper surface of the raised fingers, the gate trenches having bottoms spaced vertically from the second epitaxial layer, and the plurality of gate trenches being interconnected;
implanting material in the first epitaxial layer at the bottoms of the gate trenches to form implanted gate areas in the gate trenches;
annealing to activate the implanted gate areas;
depositing a gate contact in communication with the implanted gate areas by depositing a thin metal layer on the implanted gate areas to reduce gate resistance wherein the step of etching the plurality of gate trenches included undercutting the portions of patterned conductive layer to prevent metal from being deposited on trench sides during the step of depositing the thin metal layer on the implanted gate areas;
depositing a source contact in communication with the portions of patterned conductive layer overlying the source areas;
and
depositing a drain contact on a second surface of the substrate structure.

7 more elements

Dependencies are inferred from the claim text.