Integrated circuit having isolated anti-fuse structures and method for fabricating the same

A memory device, comprising:

• an address bus;
• a control bus;
• a data bus;
• an address decoder coupled to the address bus;
• a control circuit coupled to the control bus;
• a read/write circuit coupled to the data bus;
• a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
• and
• an anti-fuse formed on a surface of a silicon substrate having a first conductivity type, the anti-fuse having a first conductive layer formed on a surface of the substrate, a dielectric layer formed on the first conductive layer, and a second conductive layer formed on the dielectric layer, the second conductive layer having a portion extending beyond the dielectric layer above the surface of the silicon substrate to which a third conductive layer is contacted, the anti-fuse including a well region formed in the silicon substrate under the portion of the second conductive layer to which the third conductive layer is contacted, the well region having a second conductivity type opposite the first conductivity type and further having a shallower more lightly doped region of the second conductivity type formed therein.

A computer system, comprising:

• a data input device;
• a data output device;
• and
• a processor coupled to the data input and output devices, the processor including a memory device that includes an anti-fuse formed on a surface of a silicon substrate having a first conductivity type, the anti-fuse having a first conductive layer formed on a surface of the substrate, a dielectric layer formed on the first conductive layer, and a second conductive layer formed on the dielectric layer, the second conductive layer having a portion extending beyond the dielectric layer above the surface of the silicon substrate to which a third conductive layer is contacted, the anti-fuse including a well region formed in the silicon substrate under the portion of the second conductive layer to which the third conductive layer is contacted, the well region having a second conductivity type opposite the first conductivity type and further having a shallower more lightly doped region of the second conductivity type formed therein.