Definition of anti-fuse cell for programmable gate array application

An anti-fuse cell in an integrated circuit device comprising:

• a first undoped silicon layer chosen from the group containing polysilicon and amorphous silicon overlying a silicon oxide layer on the surface of a semiconductor substrate;
• an insulating layer overlying said first undoped silicon layer and contacting said semiconductor substrate at the bottom of an opening through said first undoped silicon and said silicon oxide layers to an active area within said semiconductor substrate;
• and
• a patterned second polysilicon layer overlying said insulating layer within said opening which forms said anti-fuse cell in said integrated circuit device.

An anti-fuse cell in an integrated circuit device comprising:

• a semiconductor substrate divided into at least one anti-fuse cell area and at least one device area separated by isolation regions;
• said anti-fuse cell area comprising:
• a first undoped silicon layer chosen from the group containing polysilicon and amorphous silicon overlying a silicon oxide layer on the surface of said semiconductor substrate;
• an insulating layer overlying said first undoped silicon layer and contacting said semiconductor substrate at the bottom of an opening through said first undoped silicon and said silicon oxide layers to an active area within said semiconductor substrate;
• and
• a patterned second polysilicon layer overlying said insulating layer within said opening which forms said anti-fuse cell;
• said device area comprising:
• semiconductor device structures including gate electrodes and source and drain regions;
• and
• electrical contacts contacting said semiconductor device structures within said device area and said anti-fuse cell in said anti-fuse cell area through openings in an insulating layer overlying said anti-fuse cell and said semiconductor device structures to complete said integrated circuit device.