Nonvolatile semiconductor memory device structure with superimposed bit lines and short-circuit metal strips

A semiconductor memory device comprising:

• a plurality of memory cells arranged in a matrix of rows and columns, each memory cell being located at an intersection of one of the rows and one of the columns, each memory cell having a control terminal coupled to one of the rows, a first terminal electrically coupled to one of the columns, and a second terminal;
• and
• a plurality of conductive strips permanently in ohmic contact with the second terminals of the memory cells and coupled to a reference voltage, the conductive strips and columns being superimposed over each other.

A nonvolatile semiconductor memory device comprising;

• a matrix of memory cells formed in a semiconductor material layer, the memory cells being located at intersections of rows and columns of the matrix, each memory cell comprising a control gate electrode connected to one of said rows, a first electrode electrically connected to one of said columns, and a second electrode, said rows comprising polysilicon strips extending parallel to each other in a first direction, said columns being formed by metal strips extending parallel to each other in a second direction orthogonal to said first direction;
• and
• a plurality of short-circuit metal strips permanently electrically connected to the second electrodes of the memory cells, said columns and said shortcircuit metal strips being respectively formed in a first metal level and a second metal level superimposed on each other and electrically insulated from each other by a dielectric layer.