Complementary junction field effect transistors
AssigneeLovoltech, Inc.
InventorHo-yuan Yu
Life of this patent
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Abstract
Junction Field Effect Transistor (JFET) offers fast switching speed than bipolar transistor since JFET is a majority carrier device. This invention comprises two normally “off” JFETs, one in N-channel and one in P-channel to form Complementary Junction Field Effect Transistors for high speed, low voltage and/or high current applications. The discrete device structure is disclosed in this invention. The integrated Complementary Junction Field Effect Transistors structure processed in standard CMOS process is disclosed in this invention. A vertical gate structure of Complementary Junction Field Effect Transistors is disclosed. Complementary Junction Field Effect Transistors structure is also disclosed in SOI substrate.
Claims23
A complementary junction field effect transistor (JFET) circuit structure comprising:
- an enhancement mode P-channel junction field effect transistor (JFET) having a Gate, Source and Drain;
- and
- an enhancement mode N-channel junction field effect transistor (JFET) having a Gate, Source and Drain;
- wherein one of either of the Drain or the Source of said enhancement mode P-channel JFET is electrically coupled to one of either of the Drain or the Source of said enhancement N-channel JFET and wherein the Gate of said enhancement mode P-channel JFET is electrically coupled to the Gate of said enhancement mode N-channel JFET.
A complementary junction field effect transistor (JFET) circuit structure comprising:
- an enhancement mode P-channel junction field effect transistor (JFET);
- an enhancement mode N-channel junction field effect transistor (JFET);
- wherein one of either of the Drain or the Source of said enhancement mode P-channel JFET is electrically coupled to one of either of the Drain or the Source of said enhancement N-channel JFET;
- and
- wherein the Gate of said enhancement mode P-channel JFET is electrically coupled to the Gate of said enhancement mode N-channel JFET;
- and
- wherein the Gate of the enhancement mode N-channel JFET comprises a plurality of electrically coupled gate elements separated by a distance W1, wherein each gate element is surrounded by a depletion region;
- wherein the Gate of the enhancement mode P-channel JFET comprises a plurality of electrically coupled gate elements separated by a distance W2, wherein each gate element is surrounded by a depletion region;
- wherein the threshold voltage for at least one of either the P-channel JFET or the N-channel JFET has been adjusted by increasing and decreasing the channel doping concentration near each depletion region surrounding each gate element and subsequently adjusting distances W1 and W2 by using an RTA thermal process.
A method of fabricating a complementary JFET circuit structure comprising the steps of:
- on a N-type substrate, forming a first plurality of gates for a N-channel JFET separated by a distance, W1, wherein each gate is surrounded by a depletion region;
- forming a P-type well on said N-type substrate;
- on said P-type well, forming a second plurality of gates for a P-channel JFET separated by a distance, W2, wherein each gate is surrounded by a depletion region;
- adjusting a threshold voltage for said N-channel JFET and said P-channel JFET by increasing and decreasing channel doping concentration near each depletion region surrounding each gate wherein increasing said channel doping concentration near each depletion region decreases said threshold voltage;
- and
- adjusting said threshold voltage by adjusting said distance W1 and said distance W2, using an RTA thermal process prior to metalization.
A method of fabricating a complementary JFET circuit structure comprising the steps of:
- on a P-type substrate, forming a first plurality of gates for a P-channel JFET separated by a distance, W2, wherein each gate is surrounded by a depletion region;
- forming a N-type well on said P-type substrate;
- on said N-type well, forming a second plurality of gates for a N-channel JFET separated by a distance, W1, wherein each gate is surrounded by a depletion region;
- adjusting a threshold voltage for said N-channel JFET and said P-channel JFET by increasing and decreasing channel doping concentration near each depletion region surrounding each gate wherein increasing said channel doping concentration near each depletion region decreases said threshold voltage;
- and
- adjusting said threshold voltage by adjusting said distance W1 and said distance W2, using an RTA thermal process prior to metalization.
Dependencies are inferred from the claim text.