Power/ground metallization routing in a semiconductor device
AssigneeNurlogic Design, Inc.
InventorsMichael J. Brunolli, Behnan Malek-Khosravi, Nurtjahya Sambawa
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Abstract
A semiconductor device and a method of laying out the same includes routing primary power and ground distributions in the second metallization layer, rather than the first metallization as is conventionally done. This improves routability in the first metallization layer while providing sufficient current handling ability in the power and ground distributions.
Claims10
A basic cell in an integrated circuit having a plurality of cells, said basic cell including:
- a first conductivity device region;
- a second conductivity device region;
- a first metal layer formed over said first and second conductivity device regions, said first metal layer comprising interconnections between devices formed in said first and second conductivity device regions and other of said plurality of cells;
- a second metal layer formed over said first metal layer, said second metal layer comprising primary power and ground distributions;
- and
- means for conducting current respectively between said primary power and ground distributions and said first and second conductivity device regions.
A layout method in an integrated circuit having a plurality of cells, each of said cells including a first conductivity device region and a second conductivity device region, said method comprising:
- providing interconnections between said cells in a first metal layer formed over said first and second conductivity device regions;
- providing primary power and ground distributions in a second metal layer formed over said first metal layer;
- and
- providing means for conducting current respectively between said primary power and ground distributions and said first and second conductivity device regions.
Dependencies are inferred from the claim text.