Flash memory having a treatment layer disposed between an interpoly dielectric structure and method of forming

Abstract

A flash memory structure and fabrication process whereby stacks of a first poly-crystalline or of an amorphous silicon material (polysilicon), having a bottom layer member of an interpoly dielectric stack, are processed for formation of a post-treatment layer over the bottom interpoly dielectric layer member. The post-treatment layer is essentially a solid material formed by a chemical reaction for purposes of improving the reliability of an interpoly dielectric stack and results in changes to the capacitor coupling ratio of the flash memory element and allows the use of new power supply and programming voltages. The post-treatment layer is formed by exposing the polysilicon stacks with the bottom interpoly dielectric layer member to a selected one of at least three ambient reagent gases. The selected ambient reagent gases and exposure of the semiconductor structure being performed in either a batch furnace, a single wafer rapid thermal anneal tool, or a plasma chamber. Then at least three ambient reagent gases are selected from a group of reagent gases consisting essentially of N2O/NO, O2/H2O/O3, and NH3/N2. Any of the ambient reagent gases may be selected and utilized in a selected fabrication tools for pre-treating the surface of the bottom interpoly dielectric stack member prior to forming the complete interpoly dielectric stack of the flash memory element. The subsequently formed interpoly dielectric stack being a modified ONO stack where the post-treatment layer is disposed between the bottom silicon dioxide layer and the silicon nitride and silicon dioxide layers.

Dependencies are inferred from the claim text.